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φ
V
CC
FWE
MD
to MD
*
2
0
RES
SWE bit
Period during which flash memory access is prohibited
(x: Wait time after setting SWE bit, y: Wait time after clearing SWE bit)*
Period during which flash memory can be programmed
(Execution of program in flash memory prohibited, and data reads other than verify operations
prohibited)
Notes: 1. Except when switching modes, the level of the mode pins (MD
by pulling the pins up or down.
2. See 22.3.6 Flash Memory Characteristics.
Wait time:
t
OSC1
t
MDS
t
MDS
SWE set
Figure 18.16 Power-On/Off Timing (Boot Mode)
Program-
ming/
erasing
Wait time:
possible
x
y
Min 0 µs
SWE cleared
2
–MD
2
Min 0 µs
) must be fixed until power-off
0
565
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