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Contention between General Register Write and Input Capture: If an input capture signal
occurs in the T
state of a general register write cycle, input capture takes priority and the write to
3
the general register is not performed. See figure 8.44.
φ
Address bus
Internal write signal
Input capture signal
16TCNT
GR
Figure 8.44 Contention between General Register Write and Input Capture
General register write cycle
T
T
1
2
GR address
M
T
3
M
275
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