Hitachi H8/3062 Hardware Manual page 677

Module Item
SCI Input Asyn-
clock chronous
cycle
Syn-
chronous
Input clock rise
time
Input clock fall
time
Input clock
pulse width
Transmit data
delay time
Receive data
setup time
(synchronous)
Receive
data hold
time (syn-
chronous)
Chip output pin
C
662
Symbol Min
t 4
Scyc
6
t 1.5
SCKr
t 1.5
SCKf
t 0.4
SCKW
t —
TXD
t 100
RXS
Clock t 100
RXH
input
Clock 0
output
R
H
Figure 22.3 Output Load Circuit
Condition
A B
Max Min Max
— 4 —
— 6 —
— 1.5 —
— 1.5 —
0.6 0.4 0.6
100 — 100
— 100 —
— 100 —
— 0 —
R
L
C = 90 pF: ports 4, 6, 8, A
C = 30 pF: ports 9, A, B, RESO
R = 2.4 k
L
R = 12 k
H
Input/output timing measurement levels
• Low: 0.8 V
• High: 2.0 V
C
Min Max Unit
4 — t
cyc
6 — t
cyc
1.5 — t
cyc
1.5 — t
cyc
0.4 0.6 t
Scyc
— 100 ns
100 — ns
100 — ns
0 — ns
to A
19
Ω
Ω
Test
Conditions
Figure 22.24
Figure 22.25
, D to D
0 15 8