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Pin
Name
Mode
PA
1, 2
7
3, 4
5
6, 7
PB
to PB
1 to 5
3
0
6, 7
PB
to PB
1 to 7
7
4
Legend:
H:
High
L:
Low
T:
High-impedance state
keep: Input pins are in the high-impedance state; output pins maintain their previous state.
DDR: Data direction register
Notes: 1 Low output only when WDT overflow causes a reset.
This RESO output function is provided only in the mask ROM version.
2 When A23E, A22E, A21E = 0 in BRCR (bus release control register).
3 When A23E, A22E, A21E = 1 in BRCR (bus release control register).
4 When A20E = 0 in BRCR (bus release control register).
5 When A20E = 1 in BRCR (bus release control register).
6 When CS7E, CS6E, CS5E, CS4E = 1 in CSCR (chip select control register).
7 When CS7E, CS6E, CS5E, CS4E = 0 in CSCR (chip select control register).
The bus cannot be released in modes 6 and 7.
Hardware
Standby
Software
Reset
Mode
Standby Mode
Keep
T
T
(SSOE = 0)
L
T
T
(SSOE = 1)
Keep
(Address output)*
T
T
(SSOE = 0)
T
(SSOE = 1)
Keep
(Otherwise)*
Keep
T
T
Keep
(CS output)*
T
T
(SSOE = 0)
T
(SSOE = 1)
H
(Otherwise)*
Keep
T
T
Keep
T
T
Keep
Bus-
Released Mode
Keep
T
4
(Address output)*
T
(Otherwise)*
Keep
5
—
6
(CS output)*
T
(Otherwise)*
Keep
7
—
Keep
Program
Execution Mode
I/O port
A
20
4
(Address output)*
A
20
5
5
(Otherwise)*
I/O port
I/O port
6
6
(CS output)*
CS
to CS
7
4
7
7
(Otherwise)*
I/O port
I/O port
I/O port
4
907
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