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IER—IRQ Enable Register
Bit
Initial value
Read/Write
ISR—IRQ Status Register
Bit
Initial value
Read/Write
Note: * Only 0 can be written to clear the flag.
808
7
6
5
IRQ5E
0
0
0
R/W
R/W
R/W
7
6
5
IRQ5F
0
0
0
R/(W)*
IRQ5 to IRQ0 flags
Bits 5 to 0
IRQ5F to IRQ0F
[Clearing conditions]
• Read IRQnF when IRQnF = 1, then write 0 in IRQnF.
• IRQnSC = 0, IRQn input is high, and interrupt exception
0
handling is being carried out.
• IRQnSC = 1 and IRQn interrupt exception handling is being
carried out.
[Setting conditions]
• IRQnSC = 0 and IRQn input is low.
1
• IRQnSC = 1 and IRQn input changes from high to low.
H'EE015
4
3
IRQ4E
IRQ3E
0
0
R/W
R/W
IRQ
to IRQ
enable
5
0
0
IRQ
to IRQ
interrupts are disabled
5
0
1
IRQ
to IRQ
interrupts are enabled
5
0
H'EE016
4
3
2
IRQ4F
IRQ3F
IRQ2F
0
0
0
R/(W)*
R/(W)*
R/(W)*
Setting and Clearing Conditions
Interrupt Controller
2
1
IRQ2E
IRQ1E
IRQ0E
0
0
R/W
R/W
R/W
Interrupt Controller
1
0
IRQ1F
IRQ0F
0
0
R/(W)*
R/(W)*
(n = 5 to 0)
0
0
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