Hitachi H8/3062 Hardware Manual page 844

TMDR—Timer Mode Register
Bit
Initial value
Read/Write
7 6
— MDF FDIR
1 0
— R/W R/W
PWM mode 0
PWM mode 1
0
1
PWM mode 2
0 Channel 2 operates normally
1 Channel 2 operates in PWM mode
Flag direction
OVF is set to 1 in TISRC when 16TCNT2
0
overflows or underflows
OVF is set to 1 in TISRC when 16TCNT2
1
overflows
Phase counting mode
0 Channel 2 operates normally
1 Channel 2 operates in phase counting mode
H'FFF62
5 4 3
— —
0 1 1
— —
0 Channel 0 operates normally
1 Channel 0 operates in PWM mode
Channel 1 operates normally
Channel 1 operates in PWM mode
16-bit timer (all channels)
2 1
PWM2 PWM1 PWM0
0 0
R/W R/W
(Initial value)
(Initial value)
(Initial value)
(Initial value)
(Initial value)
0
0
R/W
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