Hitachi H8/3062 Hardware Manual page 445

Single-chip microcomputer

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Table of Contents

No parity error

Parity error

D0 to D7: Data bits

Error signal

The operating sequence is as follows.

1. When the data line is not in use it is in the high-impedance state, and is fixed high with a pull-

up resistor.

2. The transmitting device starts transfer of one frame of data. The data frame starts with a start

bit (Ds, low-level), followed by 8 data bits (D0 to D7) and a parity bit (Dp).

3. With the smart card interface, the data line then returns to the high-impedance state. The data

line is pulled high with a pull-up resistor.

4. The receiving device carries out a parity check. If there is no parity error and the data is

received normally, the receiving device waits for reception of the next data. If a parity error

occurs, however, the receiving device outputs an error signal (DE, low-level) to request

retransmission of the data. After outputting the error signal for the prescribed length of time,

the receiving device places the signal line in the high-impedance state again. The signal line is

pulled high again by a pull-up resistor.

5. If the transmitting device does not receive an error signal, it proceeds to transmit the next data

frame. If it receives an error signal, however, it returns to step 2 and transmits the same data

Output from transmitting device

Figure 13.3 Smart Card Interface Data Format