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Block Diagram of Channel 2: Figure 8.3 is a block diagram of channel 2
TCLKA to TCLKD
φ, φ/2, φ/4, φ/8
Legend:
16TCNT2:
Timer counter 2 (16 bits)
GRA2, GRB2:
General registers A2 and B2 (input capture/output compare registers)
(16 bits × 2)
TCR2:
Timer control register 2 (8 bits)
TIOR2:
Timer I/O control register 2 (8 bits)
Clock selector
Comparator
Figure 8.3 Block Diagram of Channel 2
Control logic
Module data bus
TIOCA
2
TIOCB
2
IMIA2
IMIB2
OVI2
221
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