Hitachi H8/3062 Hardware Manual page 393

Single-chip microcomputer
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Bit 2
TEND
0
1
For Smart Card Interface (SMIF Bit in SCMR Set to 1): Indicates that when the last bit of a
serial character was transmitted TDR did not contain valid transmit data, so transmission has
ended. The TEND flag is a read-only bit and cannot be written.
Bit 2
TEND
0
1
Note: etu: Elementary time unit (time required to transmit one bit)
Bit 1—Multiprocessor bit (MPB): Stores the value of the multiprocessor bit in the receive data
when a multiprocessor format is used in asynchronous mode. MPB is a read-only bit, and cannot
be written.
Bit 1
MPB
0
1
Note: * If the RE bit in SCR is cleared to 0 when a multiprocessor format is selected, MPB retains
its previous value.
Description
Transmission is in progress
[Clearing condition]
Read TDRE when TDRE = 1, then write 0 in TDRE
End of transmission
[Setting conditions]
The chip is reset or enters standby mode
The TE bit in SCR is cleared to 0
TDRE is 1 when the last bit of a 1-byte serial transmit character is
transmitted
Description
Transmission is in progress
[Clearing condition]
Read TDRE when TDRE = 1, then write 0 in TDRE
End of transmission
[Setting conditions]
The chip is reset or enters standby mode
The TE bit is cleared to 0 in SCR and the FER/ERS bit is also cleared to 0
TDRE is 1 and FER/ERS is 0 (normal transmission) 2.5 etu (when GM = 0)
or 1.0 etu (when GM = 1) after a 1-byte serial character is transmitted
Description
Multiprocessor bit value in receive data is 0*
Multiprocessor bit value in receive data is 1
(Initial value)
(Initial value)
(Initial value)
375

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