Module Item
SCI
Input clock
cycle
Input clock rise time
Input clock fall time
Input clock pulse width t
Transmit data delay
time
Receive data setup
time (synchronous)
Receive
data hold
time (syn-
chronous)
H8/3062F-ZTAT or
H8/3062F-ZTAT
R-mask version
output pin
680
Symbol
Asyn-
t
Scyc
chronous
Syn-
t
Scyc
chronous
t
SCKr
t
SCKf
SCKW
t
TXD
t
RXS
Clock
t
RXH
input
Clock
output
C
R
H
Figure 22.6 Output Load Circuit
Condition
A
Min
Max
Min
4
—
4
6
—
6
1.5
—
1.5
1.5
—
1.5
0.4
0.6
0.4
—
100
—
100
—
100
100
—
100
0
—
0
R
L
C = 90 pF: ports 1 to 6, and 8
C = 30 pF: ports 9, A, B
R = 2.4 k
R = 12 k
Input/output timing measurement
levels
• Low: 0.8 V
• High: 2.0 V
B
Test
Max
Unit
Conditions
—
t
Figure 22.24
cyc
—
t
cyc
—
t
cyc
—
t
cyc
0.6
t
Scyc
100
ns
Figure 22.25
—
ns
—
ns
—
ns
Ω
L
Ω
H