Hitachi H8/3062 Hardware Manual page 314

Table 9.3 Operation of Channels 0 and 1 when Bit ICE is Set to 1 in 8TCSR1 Register
Register
Register Function
TCORA0 Compare match
operation
TCORB0 Compare match
operation
TCORA1 Compare match
operation
TCORB1 Input capture
operation
Table 9.4 Operation of Channels 2 and 3 when Bit ICE is Set to 1 in 8TCSR3 Register
Register
Register Function
TCORA2 Compare match
operation
TCORB2 Compare match
operation
TCORA3 Compare match
operation
TCORB3 Input capture
operation
Status Flag Change
CMFA changed from 0
to 1 in 8TCSR0 by
compare match
CMFB not changed
from 0 to 1 in 8TCSR0
by compare match
CMFA changed from 0
to 1 in 8TCSR1 by
compare match
CMFB changed from 0
to 1 in 8TCSR1 by
input capture
Status Flag Change
CMFA changed from 0
to 1 in 8TCSR2 by
compare match
CMFB not changed
from 0 to 1 in 8TCSR2
by compare match
CMFA changed from 0
to 1 in 8TCSR3 by
compare match
CMFB changed from 0
to 1 in 8TCSR3 by
input capture
Timer Output
Capture Input
TMO output
0
controllable
No output from
TMO
0
TMIO is dedicated
1
input capture pin
TMIO is dedicated
1
input capture pin
Timer Output
Capture Input
TMO output
2
controllable
No output from
TMO
2
TMIO is dedicated
3
input capture pin
TMIO is dedicated
3
input capture pin
Interrupt Request
CMIA0 interrupt request
generated by compare
match
CMIB0 interrupt request
not generated by compare
match
CMIA1 interrupt request
generated by compare
match
CMIB1 interrupt request
generated by input
capture
Interrupt Request
CMIA2 interrupt request
generated by compare
match
CMIB2 interrupt request
not generated by compare
match
CMIA3 interrupt request
generated by compare
match
CMIB3 interrupt request
generated by input
capture
295