Cpu Interface; 16-Bit Accessible Registers - Hitachi H8/3062 Hardware Manual

8.3

CPU Interface

8.3.1

16-Bit Accessible Registers

The timer counters (16TCNTs), general registers A and B (GRAs and GRBs) are 16-bit registers,
and are linked to the CPU by an internal 16-bit data bus. These registers can be written or read a
word at a time, or a byte at a time.
Figures 8.4 and 8.5 show examples of word read/write access to a timer counter (16TCNT).
Figures 8.6 to 8.9 show examples of byte read/write access to 16TCNTH and 16TCNTL.
On-chip data bus
H
CPU L
Figure 8.4 16TCNT Access Operation [CPU → 16TCNT (Word)]
On-chip data bus
H
CPU L
Figure 8.5 Access to Timer Counter (CPU Reads 16TCNT, Word)
244
Bus interface
Bus interface
16TCNTH 16TCNTL
16TCNTH 16TCNTL
H
Module
L
data bus
H
Module
L
data bus