Test-Logic-Reset State; Run-Test/Idle State; Select-Dr-Scan State - Intel Quark SoC X1000 Core Developer's Manual

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Testability—Intel Quark Core
Figure 134. TAP Controller State Diagram
B.3.1.1

Test-Logic-Reset State

In this state, the test logic is disabled so that normal operation of the device can
continue unhindered. This is achieved by initializing the instruction register such that
the IDCODE instruction is loaded. No matter what the original state of the controller,
the controller enters Test-Logic-Reset state when the TMS input is held high (1) for at
least five rising edges of TCK. The controller remains in this state while TMS is high.
The TAP controller is also forced to enter this state at power-up.
B.3.1.2

Run-Test/Idle State

A controller state between scan operations. Once in this state, the controller remains in
this state as long as TMS is held low. For instruction not causing functions to execute
during this state, no activity occurs in the test logic. The instruction register and all test
data registers retain their previous state. When TMS is high and a rising edge is applied
to TCK, the controller moves to the Select-DR state.
B.3.1.3

Select-DR-Scan State

This is a temporary controller state. The test data register selected by the current
instruction retains its previous state. If TMS is held low and a rising edge is applied to
TCK when in this state, the controller moves into the Capture-DR state, and a scan
sequence for the selected test data register is initiated. If TMS is held high and a rising
edge is applied to TCK, the controller moves to the Select-IR-Scan state. The
instruction does not change in this state.
October 2013
Order Number: 329679-001US
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Intel Quark SoC X1000 Core
Developer's Manual
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