Interrupted Burst Cycles; Burst Cycle Showing Order Of Addresses - Intel Quark SoC X1000 Core Developer's Manual

®
Bus Operation—Intel Quark Core
Figure 94.

Burst Cycle Showing Order of Addresses

CLK
ADS#
A31–A2
RDY#
BRDY#
KEN#
BLAST#
DATA
The sequences shown in
systems with 32-bit data buses. The sequence applies to all bursts, regardless of
whether the purpose of the burst is to fill a cache line, perform a 64-bit read, or
perform a pre-fetch. If either BS8# or BS16# is asserted, the Intel
Core completes the transfer of the current 32-bit word before progressing to the next
32-bit word. For example, a BS16# burst to address 4 has the following order:
4-6-0-2-C-E-8-A.
10.3.4.3

Interrupted Burst Cycles

Some memory systems may not be able to respond with burst cycles in the order
defined in
a burst cycle to be interrupted at any time. The Intel
automatically generates another normal bus cycle after being interrupted to complete
the data transfer. This is called an interrupted burst cycle. The external system can
respond to an interrupted burst cycle with another burst cycle.
The external system can interrupt a burst cycle by asserting RDY# instead of BRDY#.
RDY# can be asserted after any number of data cycles terminated with BRDY#.
An example of an interrupted burst cycle is shown in
X1000 Core immediately asserts ADS# to initiate a new bus cycle after RDY# is
asserted. BLAST# is deasserted one clock after ADS# begins the second bus cycle,
indicating that the transfer is not complete.
October 2013
Order Number: 329679-001US
Ti T1
†
To Processor
Table 67
Table 67. To support these systems, the Intel
T2 T2
104 100
† †
accommodate systems with 64-bit buses as well as
®
®
Quark SoC X1000 Core
Figure
T2 T2
10C 108
†
†
242202-039
®
Quark SoC X1000
Quark SoC X1000 Core allows
®
95. The Intel Quark SoC
®
Intel Quark SoC X1000 Core
Developer's Manual
Ti
207