Interfacing With 8-, 16-, And 32-Bit Memories; Next Byte Enable Values For Bsx# Cycles; Data Pins Read With Different Bus Sizes - Intel Quark SoC X1000 Core Developer's Manual

®
Bus Operation—Intel Quark Core
The external system must contain buffers to enable the Intel
to read and write data on the appropriate data bus pins.
lines to which the Intel
valid combination of byte enables and bus sizing options.
Table 62.

Next Byte Enable Values for BSx# Cycles

BE3# BE2#
1
1
1
0
1
1
0
1
0
0
Note: "N" means that another bus cycle is not required to satisfy the request.
Table 63.

Data Pins Read with Different Bus Sizes

BE3#
1
1
1
0
1
1
0
1
0
0
Valid data is only driven onto data bus pins corresponding to asserted byte enables
during write cycles. Other pins in the data bus are driven but they contain no valid
data. The Intel
data bus for which the corresponding byte enable is deasserted.
10.1.3

Interfacing with 8-, 16-, and 32-Bit Memories

Note: The implementation of Intel
data mode only.
October 2013
Order Number: 329679-001US
®
Quark SoC X1000 Core expects data to be returned for each
Current
BE1# BE0# BE3#
1 1 0 N
1 0 0 1
0 0 0 1
0 0 0 0
1 0 1 N
0 0 1 1
0 0 1 0
0 1 1 N
0 1 1 0
1 1 1 N
BE2# BE1# BE0#
1 1 0
1 0 0
0 0 0
0 0 0
1 0 1
0 0 1
0 0 1
0 1 1
0 1 1
1 1 1
®
Quark SoC X1000 Core does not duplicate write data onto parts of the
®
Quark Core on Intel
Table 63
Next with
BE2# BE1# BE0# BE3#
N N N
1 0 1
0 0 1
0 0 1
N N N
0 1 1
0 1 1
N N N
1 1 1
N N N
w/o BS8#/BS16#
D[7:0]
D[15:0]
D[23:0]
D[31:0]
D[15:8]
D[23:8]
D[31:8]
D[23:16]
D[31:16]
D[31:24]
®
Quark SoC X1000 supports 32-bit
®
Quark SoC X1000 Core
shows the data bus
Next with BS16#
BE2# BE1# BE0#
N N N N
N N N N
1 0 1 1
0 0 1 1
N N N N
1 0 1 1
0 0 1 1
N N N N
N N N N
N N N N
w BS8# w BS16#
D[7:0] D[7:0]
D[7:0] D[15:0]
D[7:0] D[15:0]
D[7:0] D[15:0]
D[15:8] D[15:8]
D[15:8] D[15:8]
D[15:8] D[15:8]
D[23:16] D[23:16]
D[23:16] D[31:16]
D[31:24] D[31:24]
®
Intel Quark SoC X1000 Core
Developer's Manual
187