Data Lines (D[31:0]); Parity; Data Parity Input/Outputs (Dp[3:0]); Parity Status Output (Pchk#) - Intel Quark SoC X1000 Core Developer's Manual

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Hardware Interface—Intel
address space (00000000H through 0000FFFFH). A[31:2] identify addresses to a 4-
byte location. BE[3:0]# identify which bytes within the 4-byte location are involved in
the current transfer.
Addresses are driven back into the Intel
cache line invalidations. The address lines are active high. When used as inputs into the
processor, A[31:4] must meet the setup and hold times t
driven during bus or address hold.
The byte enable outputs, BE[3:0]#, determine which bytes must be driven valid for
read and write cycles to external memory.
• BE3# applies to D[31:24]
• BE2# applies to D[23:16]
• BE1# applies to D[15:8]
• BE0# applies to D[7:0]
BE[3:0]# can be decoded to generate A0, A1 and BHE# signals used in 8- and 16-bit
systems (see
are not driven during bus hold.
9.2.3

Data Lines (D[31:0])

The bidirectional lines D[31:0] form the data bus for the Intel
D[7:0] define the least significant byte and D[31:24] the most significant byte. Data
transfers to 8- or 16-bit devices are enabled using the data bus sizing feature, which is
controlled by the BS8# or BS16# input signals. D[31:0] are active high. For reads,
D[31:0] must meet the setup and hold times t
read cycles and bus hold.
9.2.4

Parity

9.2.4.1

Data Parity Input/Outputs (DP[3:0])

DP[3:0] are the data parity pins for the processor. There is one pin for each byte of the
data bus. Even parity is generated or checked by the parity generators/checkers. Even
parity means that there are an even number of high inputs on the eight corresponding
data bus pins and parity pin.
Data parity is generated on all write data cycles with the same timing as the data
driven by the Intel
back to the Intel
information to ensure that the correct parity check status is indicated by the Intel
Quark SoC X1000 Core.
The values read on these pins do not affect program execution. It is the responsibility
of the system to take appropriate actions if a parity error occurs.
Input signals on DP[3:0] must meet setup and hold times t
operation.
9.2.4.2

Parity Status Output (PCHK#)

Parity status is driven on the PCHK# pin, and a parity error is indicated by this pin
being low. For read operations, PCHK# is driven the clock after ready to indicate the
parity status for the data sampled at the end of the previous clock. Parity is checked
during code reads, memory reads and I/O reads. Parity is not checked during interrupt
acknowledge cycles. PCHK# only checks the parity status for enabled bytes as
October 2013
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Quark Core
Table 64 in Chapter 10.0, "Bus
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Quark SoC X1000 Core. Even parity information must be driven
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Quark SoC X1000 Core on these pins with the same timing as read
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Quark SoC X1000 Core over A[31:4] during
and t
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Operation"). BE[3:0]# are active low and
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and t . D[31:0] are not driven during
22 23
and t
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. A[31:2] are not
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Quark SoC X1000 Core.
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for proper
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Intel Quark SoC X1000 Core
Developer's Manual
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