Translation Lookaside Buffer (Tlb) Testing; Translation Lookaside Buffer Organization; Tr4 Definition For Standard And Enhanced Bus Modes For The Write-Back Enhanced; Tr5 Definition For Standard And Enhanced Bus Modes For The Write-Back Enhanced - Intel Quark SoC X1000 Core Developer's Manual

Figure 130. TR4 Definition for Standard and Enhanced Bus Modes for the Write-Back
Enhanced Intel
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Figure 131. TR5 Definition for Standard and Enhanced Bus Modes for the Write-Back
Enhanced Intel
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
B.2

Translation Lookaside Buffer (TLB) Testing

The Intel
for assembly language testing of the TLB.
B.2.1

Translation Lookaside Buffer Organization

The Intel
entries. The TLB is logically split into three blocks shown in
The data block is physically split into four arrays, each with space for eight entries. An
entry in the data block is 22 bits wide containing a 20-bit physical address and two bits
for the page attributes. The page attributes are the PCD (page cache disable) bit and
the PWT (page write-through) bit. Refer to
PWT bits.
The tag block is also split into four arrays, one for each of the data arrays. A tag entry
is 21 bits wide containing a 17-bit linear address and four protection bits. The
protection bits are valid (V), user/supervisor (U/S), read/write (R/W) and dirty (D).
The third block contains eight three bit quantities used in the pseudo least recently
used (LRU) replacement algorithm. These bits are called the LRU bits. Unlike the on-
chip cache, the TLB replaces a valid line even when there is an invalid line in a set.
®
Intel

Quark SoC X1000 Core

Developer's Manual
300
®
Quark SoC X1000 Core
TAG
TAG
®
Quark SoC X1000 Core
reserved
reserved
®
Quark SoC X1000 Core TLB testability hooks are designed to be accessible
®
Quark SoC X1000 Core TLB is 4-way set associative and has space for 32
®
Intel
8 7 6 5 4 3
VALID
r
V
LRU
(SET)
r
r r
LRU
8 7 6 5 4 3
Set Addr
S
r
Set Addr
L
F
Figure
Section 7.6 for a discussion of the PCD and
Order Number: 329679-001US
Quark Core—Testability
2 1 0
Standard
r
Bus Mode
TR4
Enhanced
V V
Bus Mode
H L
TR4
2 1 0
Standard
ENT CTL
Bus Mode
TR5
Enhanced
ENT CTL
Bus Mode
TR5
132.
October 2013