Write-Back Enhanced Intel Management Mode And Cache Flushing; Non-Cached Smm; Cache Flushing (Non-Overlaid Smram) - Intel Quark SoC X1000 Core Developer's Manual

Figure 67.

Non-Cached SMM

SMI#
SMIACT#
KEN#
FLUSH#
8.6.2.1 Write-Back Enhanced Intel
Management Mode and Cache Flushing
Regardless of the on-chip cache mode (i.e., write-through or write-back) it is
recommended that SMRAM be non-overlaid. This provides the greatest freedom for
caching both SMRAM and normal memory, provides a simplified memory controller
design, and eliminates the performance penalty of flushing.
In general, cache flushing is not required when the SMRAM and normal memory are not
overlaid.
when the SMRAM is not overlaid with normal memory space.
SMRAM can not be cached as write-back lines. If SMRAM is cached, it should be cached
only as write-through lines. This is because dirty lines can not be written back to
SMRAM upon exit from SMM. The de-assertion of SMIACT# signals that the processor is
exiting SMM, and is used to assert FLUSH#. By the time the write back of dirty lines
occurs, SMIACT# would already be inactive, so the SMRAM could no longer be decoded.
When the SMRAM is cached as write-through, this problem does not occur.
Table 47.

Cache Flushing (Non-Overlaid SMRAM)

Normal Memory
Cacheable
No
No
WT
WB
WT
WB
Coherency requirements must be met when normal memory is cached in write-back
mode. In this case, the snoop and replacement write-backs that occur during SMM
must go to normal memory, even though SMIACT# is active. This requirement is
compatible with SMM security requirements, because these write backs can not decode
the SMRAM, and the memory system must be able to handle this situation properly.
®
Intel Quark SoC X1000 Core
Developer's Manual
144
Intel
State
Slave
Table 47 gives the cache flushing requirements for entering and exiting SMM,
SMRAM Cacheable
No
WT
No
No
WT
WT
®
Quark Core—System Management Mode (SMM) Architectures
SMM
Handler Resume
RSM
®
Quark SoC X1000 Core System
FLUSH Entering SMM
No
No
No
No, but Snoop WBs must go to Normal
Memory Space.
No
No, but Snoop and Replacement WBs
must go to normal memory space.
State Normal
Cycle
A5239-01
October 2013
Order Number: 329679-001US