Intel Quark SoC X1000 Core Developer's Manual page 289

Instruction Set Summary—Intel
Table 94. Floating-Point Clock Count Summary (Sheet 7 of 8)
Instruction
FABS = Absolute value of ST(0)
FCHS = Change Sign of ST(0)
TRANSCENDENTAL
FCOS = Cosine of ST(0)
FPTAN = Partial Tangent of ST(0)
FPATAN = Partial Arctangent
FSIN = Sine of ST(0)
FSINCOS = Sine and Cosine of ST(0)
F2XM1 = 2ST(0)-1
FYL2X = ST(1) x log2(ST(0))
FYL2XP1 = ST(1) x log2(ST(0) + 1.0)
PROCESSOR CONTROL
FINIT = Initialize FPU
FSTSW AX = Store status word into AX
FSTSW = Store status word into memory
FLDCW = Load control word
FSTCW = Store control word
Notes:
1. If operand is 0 clock counts = 27.
2. If operand is 0 clock counts = 28.
3. If CW.PC indicates 24 bit precision then subtract 38 clocks.
If CW.PC indicates 53 bit precision then subtract 11 clocks.
4. If there is a numeric error pending from a previous instruction, add 17 clocks.
5. If there is a numeric error pending from a previous instruction, add 18 clocks.
6. The INT pin is polled several times while this function is executing to ensure short interrupt latency.
7. If ABS(operand) is greater than π/4 then add n clocks, where n=(operand/(π/4)).
October 2013
Order Number: 329679-001US
®
Quark Core
Format
11011 001 : 1110 0001
11011 001 : 1110 0000
11011 001 : 1111 1111
11011 001 : 1111 0010
11011 001 : 1111 0011
11011 001 : 1111 1110
11011 001 : 1111 1011
11011 001 : 1111 0000
11011 001 : 1111 0001
11011 001 : 1111 1001
11011 001 : 1110 0011
11011 111 : 1110 0000
11011 101 : mod 111 r/m : s-i-b/disp.
11011 001 : mod 101 r/m : s-i-b/disp.
11011 001 : mod 111 r/m : s-i-b/disp.
Cache Hit Concurrent
Penalty
Avg (Lower
if
Range... Avg (Lower
Cache
Upper Range- Upper
Miss
Range)
3
6
241(193-279)
244(200-273)
289(218-303)
241(193-279)
291(243-329)
242(140-279)
311(196-329)
313(171-326)
17
3
3
4 2
3
®
Intel Quark SoC X1000 Core
Execution
Notes
Range)
2 6,7
70 6,7
5(2-17) 6
2 6,7
2 6,7
2 6
13 6
13 6
4
5
5
5
Developer's Manual
289