Intel Quark SoC X1000 User Manual
Debug operations
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Also See for Quark SoC X1000:
- Developer's manual (311 pages) ,
- Design manual (186 pages) ,
- Software user's manual (54 pages)
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Summary of Contents for Intel Quark SoC X1000
- Page 1 ® Intel Quark SoC X1000 Debug Operations User Guide January 2014 Order Number: 329866-002US...
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Page 2: Table Of Contents
Contents Contents Introduction .....................4 Terminology ..................5 Related Documents .................5 JTAG Interface ....................7 SKU-Based JTAG Debug Capability ............7 CLTAPC Instruction Table ................7 CLTAPC Data Register Table ..............8 2.3.1 CLIDCODE ................8 2.3.2 CLBYPASS ................8 2.3.3 CLTAPC_SELECT ...............8 2.3.4 CLTAPC_CPU_VPREQ ..............9 2.3.5 CLTAPC_CPU_TAPSTATUS ............10 2.3.6 CLTAPC_CPU_VPRDY ............... - Page 3 Single Step ..................25 5.12 Redirections into Probe Mode ..............25 5.12.1 Shutdown Break ..............25 Figures ® Figure 1. Intel Quark SoC X1000 ..................4 Tables Table 1. Terminology .....................5 Table 2. Related Documents ...................5 Table 3. CLTAPC TAP Instructions ..................7 Table 4.
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Page 4: Introduction
Architecture (IA) SoC for deeply embedded applications. The SoC integrates the ® Intel Quark SoC X1000 Core plus all the required hardware components to run off- the-shelf operating systems and to leverage the vast x86 software ecosystem. For ® details, see the Intel Quark SoC X1000 Datasheet. -
Page 5: Terminology
Table 2. Related Documents Title and Location Document # ® Intel Quark SoC X1000 Datasheet 329676 https://communities.intel.com/docs/DOC-21828 ® Intel Quark SoC X1000 Core Hardware Reference Manual 329678 https://communities.intel.com/docs/DOC-21825 ® Intel Quark SoC X1000 Core Developer’s Manual 329679 https://communities.intel.com/docs/DOC-21826 Order Number: 329866-002US... - Page 6 Introduction Title and Location Document # ® Intel 64 and IA-32 Architectures Software Developer Manuals contain details on architectural registers: Multiple http://www.intel.com/content/www/us/en/processors/architectures- volumes software-developer-manuals.html Order Number: 329866-002US...
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Page 7: Jtag Interface
® The Intel Quark SoC X1000 has the standard set of JTAG pins, TCLK, TDI, TDO, TMS, and TRST# on the package which are routed to a debug header on the system board. The SoC exposes a single IEEE compliant TAP by default, called the ‘Chip-Level TAP Controller’... -
Page 8: Cltapc Data Register Table
Software to confirm there is a working JTAG connection to the board and to confirm the identity of the SoC. ® The Intel Quark SoC X1000 IDCODE is 0x0E681013. 2.3.2 CLBYPASS This is the IEEE standard BYPASS data register; it is one bit in size. -
Page 9: Cltapc_Cpu_Vpreq
Debug Software the ability to use some PREQ based debug features when connected using JTAG pins alone. This data register contains bits that control the assertion of the internal ‘PREQ’ signal ® to the Intel Quark SoC X1000 Core and reset break behavior. Table 6. CLTAPC_CPU_VPREQ CLTAPC_CPU_VPREQ Bit Number... -
Page 10: Cltapc_Cpu_Tapstatus
JTAG Interface 2.3.5 CLTAPC_CPU_TAPSTATUS This data register contains status bits related to the Run Control features in the CLTAPC_CPU_VPREQ register. Table 7. CLTAPC_CPU_TAPSTATUS CLTAPC_CPU_TAPSTATUS Bit Number Name Reset Value Comments PREQ was asserted via one vpreq_asserted 1'b0 of the sources in CPU_VPREQ PRDY was asserted by the prdy_asserted... -
Page 11: Cltapc_Tapnw_Status
JTAG Interface Table 8. CLTAPC_TAPNW_STATUS CLTAPC_TAPNW_STATUS Bit Number Name Reset Comments Value Returns 1 when the cltapnw_en[CPUCORETAP_SEL] IA Core TAP is in the JTAG Chain 31:1 RESERVED RESERVED S5_power_ok S5_power_ok Status S3_power_ok S3_power_ok Status S0_power_ok S0_power_ok Status When the SoC is in S0, this bit must be 1 jtag_valid before the Core TAP... -
Page 12: Putting It All Together
Initial JTAG Discovery There are two methods available for Debug Software to confirm that it has a good ® connection to the Chip-Level TAP Controller before moving on to debug the Intel Quark SoC X1000 Core. Using a TAP Reset ... -
Page 13: Verify Core Idcode
Putting It All Together Verify Core IDCODE After completing the steps above, the Debug Software can then verify that the Core TAP is in the JTAG chain. The 8 bit IR Opcode for the Core IDCODE data register is 0x2. The Core IDCODE value is 0x18289013. Order Number: 329866-002US... -
Page 14: Jtag Interface
JTAG Interface JTAG Interface TAP Instruction Table ® The Intel Quark SoC X1000 Core TAP uses an 8-bit instruction register. The following table describes all IR opcode encodings. Table 9. TAP Instructions Description DR Size Values IR Opcode Command (Bits) -
Page 15: Run Control
WRSUBPIR instruction into the TAP that then transfers the instruction bytes to the fetch unit. Probe Mode Entry on Intel processors is an interrupt/exception style event and is prioritized with other events. The priority is very low. Probe Mode Entry Probe Mode may be entered asynchronously (from the Core’s perspective) by the... -
Page 16: Probe Mode Exit
® capability must be used. The Intel Quark SoC X1000 Core supports reset break with two mechanisms. The first option depends on the PREQ# and PRDY# signals being connected to the Hardware Probe. The second option is available for when the Debug Tool is connected using only the JTAG pins. -
Page 17: Accessing Architectural Registers
Run Control Bit Field Description Probe Mode Request. Held high on Enter Probe Mode Request, reset once register state has been saved to shadow SRAM. Probe Mode Ready, this is a copy of the PRDY# signal. Since PRDY# is pulsed for a short number of clocks this may never be seen as ‘1. -
Page 18: Eip Management
5.6.3.1 EIP and Software Breakpoints ® Software breakpoints behave as instruction traps in the Intel Quark SoC X1000 Core. After entering Probe Mode due to a software break point trigger, the EIP register points to the instruction immediately after the 0xF1 opcode used for the breakpoint. -
Page 19: Register Read
Run Control 5.6.5 Register Read The template to read a register: 1. Find the PIR value for the desired register in Table 11 below. Use WRITEPIR to shift in the 64-bit value from the table. Shift in SUBMITPIR TAP instruction. 2. -
Page 20: Checking For Halt State
SRAM and checking bit 16. If bit 16 is 1, the core is in the HALT state. 5.6.9 Pseudo Opcodes for Architectural Register Access Each register in Table 11 is described in detail in the Intel Software Developer’s Manuals here: http://www.intel.com/content/www/us/en/processors/architectures- software-developer-manuals.html Order Number: 329866-002US... -
Page 21: Probe Mode Control Register
Run Control Table 11. Register Access PIR Values Register 64 Bit PIR Value Register 64 Bit PIR Value Register 64 Bit PIR Value 0x000000001D660000 TSSlimit 0x000000181D660000 CSlimit 0x0000000C1D660000 0x000000801D660000 IDTar 0x000000981D660000 ESar 0x0000008C1D660000 EFLAGS 0x000000401D660000 IDTbase 0x000000581D660000 ESbase 0x0000004C1D660000 0x000000C01D660000 IDTlimit 0x000000D81D660000 ESlimit... -
Page 22: Accessing Model Specific Registers (Msr)
Submit a ‘wrmsr’ instruction to the core via WRITEPIR and SUBMITPIR. Reading and Writing Memory ® Memory may be read and written using the Intel Quark SoC X1000 Core by direct injection of the macro-instructions via the TAP’s PIR register. The core will: 1. -
Page 23: Ds Selector
Run Control 5.7.1.1 DS Selector The DS selector must be changed before debug software can access the full 4GB address space while in Probe Mode. Prior to any memory access, the registers listed in the following table must be set to the values specified for each. Debug software must take care to read these registers after Probe Mode entry and cache the values so that they may be restored prior to Probe Mode exit. -
Page 24: Memory Read
® The Intel Quark SoC X1000 Core supports I/O port reads and writes using the IN and OUT instructions submitted to the core via the TAP. Note: The CR0.PG bit must be 0 prior to using the PIR TAP instructions to submit I/O read and write instructions. -
Page 25: Hardware Breakpoints
3. Set bit 0 in PMCR to convert the #DB exception to a Probe Mode entry. 5.10 Software Breakpoints ® To determine if an instance of the Intel Quark SoC X1000 Core supports software breakpoints, check bit 4 in the TAPSTATUS register. If the bit is ‘1, the core supports software breakpoints. -
Page 26: Revision History
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548-4725, or go to: http://www.intel.com/design/literature.htm...