Tlb Test Registers; Meaning Of A Pair Of Tr6 Protection Bits; Tr6 Operation Bit Encoding - Intel Quark SoC X1000 Core Developer's Manual

Figure 133. TLB Test Registers
31
31
The seven TLB tag protection bits are described below.
V:
D,D#: The dirty bit for/from the TLB entry
U,U#: The user/supervisor bit for/from the TLB entry
W,W#: The read/write bit for/from the TLB entry
Two bits are used to represent the D, U/S and R/W bits in the TLB tag to permit the
option of a forced miss or hit during a TLB lookup operation. The forced miss or hit
occurs regardless of the state of the actual bit in the TLB. The meaning of these pairs of
bits is given in
The operation bit in TR6 determines whether the TLB test operation is a write or a
lookup. The function of the operation bit is given in
Table 98.

Meaning of a Pair of TR6 Protection Bits

TR6 Protection Bit
(B)
Table 99.
®
Intel Quark SoC X1000 Core
Developer's Manual
302
Linear Address
Physical Address
The valid bit for this TLB entry
Table 98.
TR6 Protection Bit#
(B#)
0 0
0 1
1 0
1 1

TR6 Operation Bit Encoding

TR6 Bit 0 TLB Operation to Be Performed
0
1
12 11 10 9 8 7 6 5
V D D# U
12 11 10 9 8 7 6 5
PCD PWT L2 Unused
L1 L0
Replacement Pointer Select (Writes)
Hit Indication (Lookup)
Table
Meaning on
TLB Write Operation
Undefined
Write 0 to TLB TAG Bit B
Write 1 to TLB TAG Bit B
Undefined
TLB Write
TLB Lookup
®
Intel Quark Core—Testability
4 3 2 1 0
TR6
TLB Command
Unused
Option
Test Register
4 3 2 1 0
TR7
TLB Data
Unused
Test Register
Replacement Pointer (Writes)
Hit Location (Lookup)
99.
Meaning on
TLB Lookup Operation
Miss any TLB TAG Bit B
Match TLB TAG Bit B if 0
Match TLB TAG Bit B if 1
Match any TLB TAG Bit B
October 2013
Order Number: 329679-001US