Task Switches To And From Virtual 8086 Mode; Transitions Through Trap And Interrupt Gates, And Iret - Intel Quark SoC X1000 Core Developer's Manual

The VM bit can be set by executing an IRET instruction only at privilege level 0, or by
any instruction or interrupt that causes a task switch in Protected Mode (with VM=1 in
the new FLAGS image). The UM bit can be cleared only by an interrupt or exception in
Virtual 8086 Mode. IRET and POPF instructions executed in Real Mode or Virtual 8086
Mode do not change the value in the VM bit.
The transition out of Virtual 8086 Mode to Protected Mode occurs only on receipt of an
interrupt or exception (such as due to a sensitive instruction). In Virtual 8086 Mode, all
interrupts and exceptions vector through the Protected Mode IDT, and enter an
interrupt handler in protected Intel
interrupt processing, the VM bit is cleared.
Because the matching IRET must occur from level 0, if an interrupt or trap gate is used
to field an interrupt or exception out of Virtual 8086 Mode, the Gate must perform an
inter-level interrupt only to level 0. Interrupt or trap gates through conforming
segments, or through segments with DPL>0, raise a GP fault with the CS selector as
the error code.
6.5.6.1

Task Switches to and from Virtual 8086 Mode

Tasks that can execute in Virtual 8086 Mode must be described by a TSS with the new
®
Intel Quark SoC X1000 Core format (TYPE 9 or 11 descriptor).
A task switch out of Virtual 8086 Mode operates exactly the same as any other task
switch out of a task with a Intel
state, including the FLAGS register with the VM bit set to 1, is stored in the TSS.
The segment registers in the TSS contain legacy segment base values rather than
selectors.
A task switch into a task described by a Intel
additional check to determine if the incoming task should be resumed in Virtual 8086
Mode. Before loading the segment register images from a Intel
Core TSS, the FLAGS image is loaded, so that the segment registers are loaded from
the TSS image as legacy segment base values. The task is now ready to resume in
Virtual 8086 Mode.
6.5.6.2

Transitions Through Trap and Interrupt Gates, and IRET

A task switch is one way to enter or exit Virtual 8086 Mode. The other method is to exit
through a trap or interrupt gate as part of handling an interrupt, and to enter as part of
executing an IRET instruction. The transition out must use a Intel
Core trap gate (Type 14) or Intel
which must point to a non-conforming level 0 segment (DPL=0) in order to permit the
trap handler to IRET back to the Virtual 8086 program. The gate must point to a non-
conforming level 0 segment to perform a level switch to level 0 so the matching IRET
can change the VM bit. The action taken for a Intel
interrupt gate if an interrupt occurs while the task is executing in Virtual 8086 Mode is
given by the following sequence:
1. Save the FLAGS register in a temp to push later. Turn off the VM and TF bits and, if
the interrupt is serviced by an Interrupt Gate, turn off the IF bit also.
2. Interrupt and trap gates must perform a level switch from level 3 (where the VM86
program executes) to level 0 (so IRET can return). This process involves a stack
switch to the stack given in the TSS for privilege level 0. Save the Virtual 8086
Mode SS and ESP registers to push in a later step. The segment register load of SS
is done as a Protected Mode segment load, because the VM bit was turned off in
step 1.
®
Intel Quark SoC X1000 Core
Developer's Manual
112
®
Intel Quark Core—Protected Mode Architecture
®
Quark SoC X1000 Core mode. That is, as part of
®
Quark SoC X1000 Core TSS. The programmer visible
®
Quark SoC X1000 Core TSS has an
®
Quark SoC X1000 Core interrupt gate (Type 15),
®
Quark SoC X1000 Core trap or
®
Quark SoC X1000
®
Quark SoC X1000
October 2013
Order Number: 329679-001US