Encoding Of Operation Direction (D) Field - Intel Quark SoC X1000 Core Developer's Manual

Table 83. Encoding of 32-Bit Address Mode ("mod r/m" Byte and "s-i-b" Byte Present)
mod base
00 000
00 001
00 010
00 011
00 100
00 101
00 110
00 111
01 000
01 001
01 010
01 011
01 100
01 101
01 110
01 111
10 000
10 001
10 010
10 011
10 100
10 101
10 110
10 111
Note: Mod field in "mod r/m" byte; ss, index,
base fields in "s-i-b" byte.
12.2.3.5

Encoding of Operation Direction (d) Field

In many two-operand instructions the d field is present to indicate which operand is
considered the source and which is the destination.
Table 84.

Encoding of Operation Direction (d) Field

d
0
1
®
Intel Quark SoC X1000 Core
Developer's Manual
260
Effective Address
DS:[EAX+(scaled index)]
DS:[ECX+(scaled index)]
DS:[EDX+(scaled index)]
DS:[EBX+(scaled index)]
SS:[ESP+(scaled index)]
DS:[d32+(scaled index)]
DS:[ESI+(scaled index)]
DS:[EDI+(scaled index)]
DS:[EAX+(scaled index)+d8]
DS:[ECX+(scaled index)+d8]
DS:[EDX+(scaled index)+d8]
DS:[EBX+(scaled index)+d8]
SS:[ESP+(scaled index)+d8]
SS:[EBP+(scaled index)+d8]
DS:[ESI+(scaled index)+d8]
DS:[EDI+(scaled index)+d8]
DS:[EAX+(scaled index)+d32]
DS:[ECX+(scaled index)+d32]
DS:[EDX+(scaled index)+d32]
DS:[EBX+(scaled index)+d32]
SS:[ESP+(scaled index)+d32]
SS:[EBP+(scaled index)+d32]
DS:[ESI+(scaled index)+d32]
DS:[EDI+(scaled index)+d32]
Direction of Operation
Register/Memory ← Register "reg" Field Indicates Source Operand; "mod r/m" or
"mod ss index base" Indicates Destination Operand
Register ← Register/Memory "reg" Field Indicates Destination Operand; "mod
r/m" or "mod ss index base" Indicates Source Operand
®
Intel Quark Core—Instruction Set Summary
ss
00
01
10
11
Index Index Register
000
001
010
011
100
101
110
111
Note: When index field is 100, indicating "no index
register," then ss field MUST equal 00. When
index is 100 and ss does not equal 00, the
effective address is undefined.
Order Number: 329679-001US
Scale Factor
x1
x2
x4
x8
EAX
ECX
EDX
EBX
no index reg†
EBP
ESI
EDI
October 2013