Page Cacheability (Pwt, Pcd); Reserved; Numeric Error Reporting (Ferr#, Ignne#); Floating-Point Error Output (Ferr#) - Intel Quark SoC X1000 Core Developer's Manual

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Hardware Interface—Intel
FLUSH# also determines whether or not the three-state test mode of the Intel
SoC X1000 Core is invoked on assertion of RESET (see
X1000 Core JTAG" on page
9.2.12

Page Cacheability (PWT, PCD)

The PWT and PCD output signals correspond to two user attribute bits in the page table
entry. When paging is enabled, PWT and PCD correspond to bits 3 and 4 of the page
table entry, respectively. For cycles that are not paged when paging is enabled (for
example I/O cycles) PWT and PCD correspond to bits 3 and 4 in Control Register 3.
When paging is disabled, the Intel
bits and assumes they are zero for the purpose of caching and driving PCD and PWT.
PCD is masked by the CD (cache disable) bit in Control Register 0 (CR0). When CD=1
(cache line fills disabled) the Intel
CD=0, PCD is driven with the value of the page table entry/directory.
The purpose of PCD is to provide a cacheable/non-cacheable indication on a page by
page basis. The Intel
in which bit 4 of the page table entry is set. PWT corresponds to the write-back bit and
can be used by an external cache to provide this functionality. PCD and PWT bits are
assigned a value of zero during Real Mode and when paging is disabled. Refer to
Section 7.6
PCD and PWT have the same timing as the cycle definition pins (M/IO#, D/C#, W/R#).
PCD and PWT are active high and are not driven during bus hold.
Note: The PWT and PCD bits function differently in the write-back mode of the Write-Back
Enhanced Intel
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Intel Quark SoC X1000 Core and Processor Page Cacheability" on page
9.2.13

RESERVED#

The RESERVED# input detects the presence of an in-circuit emulator, then powers
down the core, and three-states all outputs of the original processor, so that the
original processor consumes very low current. This state is known as Reserved Power
Down Mode. RESERVED# is active low and sampled at all times, including after power-
up and during reset.
9.2.14

Numeric Error Reporting (FERR#, IGNNE#)

To allow PC-type floating-point error reporting, Intel
two pins, FERR# and IGNNE#.
9.2.14.1

Floating-Point Error Output (FERR#)

The processor asserts FERR# when an unmasked floating-point error is encountered.
FERR# can be used by external logic for PC-type floating-point error reporting. FERR#
is active low and is not floated during bus hold.
In some cases, FERR# is asserted when the next floating-point instruction is
encountered. In other cases, it is asserted before the next floating-point instruction is
encountered, depending on the execution state of the instruction that caused the
exception.
The following class of floating-point exceptions assert FERR# at the time the exception
occurs (i.e., before encountering the next floating-point instruction):
October 2013
Order Number: 329679-001US
Quark Core
304).
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Quark SoC X1000 Core does not perform a cache fill to any page
for a discussion of non-cacheable pages.
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Quark SoC X1000 Cores (see
Section B.3, "Intel
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Quark SoC X1000 Core ignores the PCD and PWT
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Quark SoC X1000 Core forces PCD high. When
Section 7.6.1, "Write-Back Enhanced
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Quark SoC X1000 Core provides
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Quark
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Quark SoC
121).
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Intel Quark SoC X1000 Core
Developer's Manual
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