Testability; On-Chip Cache Testing; Cache Testing Registers Tr3, Tr4 And Tr5 - Intel Quark SoC X1000 Core Developer's Manual

Appendix B Testability
This appendix contains the following subsections:
• Section B.1, "On-Chip Cache Testing" on page 296
• Section B.2, "Translation Lookaside Buffer (TLB) Testing" on page 300
• Section B.3, "Intel
B.1

On-Chip Cache Testing

The on-chip cache testability hooks are designed to be accessible for assembly
language testing of the cache.
The Intel
For testability writes, data must be written to the cache fill buffer before it can be
written to a location in the cache. Data must be read from a cache location into the
cache read buffer before the processor can access the data. The cache fill and cache
read buffer are both 128 bits wide.
B.1.1

Cache Testing Registers TR3, TR4 and TR5

Figure 129
Cache Status Test Register (TR4), and Cache Control Test Register (TR5). External
access to these registers is provided through MOV reg, TREG and MOV TREG, reg
instructions.
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Figure 129. Intel Quark SoC X1000 Core Cache Test Registers
31
31
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Intel Quark SoC X1000 Core
Developer's Manual
296
®
Quark SoC X1000 Core JTAG" on page 304
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Quark SoC X1000 Core contains a cache fill buffer and a cache read buffer.
shows the three cache testing registers: Cache Data Test Register (TR3),
Tag
Unused
Data
12 11 10 9 8 7 6 5
LRU Bits Valid Bits
(used only (used only
during reads) during reads)
12 11 4 3
Entry
Set Select
Select
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Intel Quark Core—Testability
0
TR3
Cache Data
Test Register
4 3 2 1 0
TR4
Cache Status
Unused
Test Register
2 1 0
TR5
Cache Control
Control
Test Register
October 2013
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