Dynamic Data Bus Sizing; Physical Memory And I/O Space Organization - Intel Quark SoC X1000 Core Developer's Manual

Figure 78.

Physical Memory and I/O Space Organization

16-bit memories are organized as arrays of two bytes each. Each two bytes begins at
addresses divisible by two. The byte enables BE[3:0]#, must be decoded to A1, BLE#
and BHE# to address 16-bit memories.
To address 8-bit memories, the two low order address bits A0 and A1 must be decoded
from BE[3:0]#. The same logic can be used for 8- and 16-bit memories, because the
decoding logic for BLE# and A0 are the same. (See
10.1.2

Dynamic Data Bus Sizing

Note: The implementation of Intel
dynamic data bus sizing. Bus width is fixed at 32 bits.
Dynamic data bus sizing is a feature that allows processor connection to 32-, 16- or 8-
bit buses for memory or I/O. The Intel
bus sizes. Transfers to or from 32-, 16- or 8-bit devices are supported by dynamically
determining the bus width during each bus cycle. Address decoding circuitry may
assert BS16# for 16-bit devices or BS8# for 8-bit devices during each bus cycle. BS8#
and BS16# must be deasserted when addressing 32-bit devices. An 8-bit bus width is
selected if both BS16# and BS8# are asserted.
BS16# and BS8# force the Intel
to complete requests larger than 16 or 8 bits. A 32-bit transfer is converted into two
16-bit transfers (or 3 transfers if the data is misaligned) when BS16# is asserted.
Asserting BS8# converts a 32-bit transfer into four 8-bit transfers.
Extra cycles forced by BS16# or BS8# should be viewed as independent bus cycles.
BS16# or BS8# must be asserted during each of the extra cycles unless the addressed
device has the ability to change the number of bytes it can return between cycles.
The Intel
cycles forced by BS8# and BS16#. A[31:2] does not change if accesses are to a 32-bit
aligned area.
for each of the valid possibilities of the byte enables on the current cycle.
The Intel
data pins. The simplest example of this function is a 32-bit aligned, BS16# read. When
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the Intel
on the data bus pins D[31:16]. The Intel
order bytes on D[15:0].
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Intel Quark SoC X1000 Core
Developer's Manual
186
FFFFFFFFH
00000003H
FFFFFFFFH
00000001H
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Quark Core on Intel
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Quark SoC X1000 Core drives the byte enables appropriately during extra
Table 62 shows the set of byte enables that is generated on the next cycle
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Quark SoC X1000 Core requires that data bytes be driven on the addressed
Quark SoC X1000 Core reads the two high order bytes, they must be driven
32-Bit Wide Organization
FFFFFFFCH
00000000H
BE3#
BE2# BE1# BE0#
16-Bit Wide Organization
FFFFFFFEH
00000000H
BHE# BLE#
Section
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Quark SoC X1000 does not support
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Quark SoC X1000 Core can access all three
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Quark SoC X1000 Core to run additional bus cycles
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Quark SoC X1000 Core expects the two low
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Intel Quark Core—Bus Operation
10.1.3)
October 2013
Order Number: 329679-001US