Pseudo Locked Cycles; Snoop Under Ahold During Pseudo-Locked Cycles; Flush Cycle - Intel Quark SoC X1000 Core Developer's Manual

If the processor is in Standard Bus mode, the processor does not issue special
acknowledge cycles in response to the FLUSH# input, although the internal cache is
invalidated. The invalidation of the cache in this case, takes only two bus clocks.
Figure 123. Flush Cycle
CLK
ADS#
RDY#
BRDY#
FLUSH#
ADDR
M/IO#
D/C#
W/R#,
BE3–0#
CACHE#
BLAST#
DATA
10.4.6

Pseudo Locked Cycles

In Enhanced Bus mode, PLOCK# is always deasserted for both burst and non-burst
cycles. Hence, it is possible for other bus masters to gain control of the bus during
operand transfers that take more than one bus cycle. A 64-bit aligned operand can be
read in one burst cycle or two non-burst cycles if BS8# and BS16# are not asserted.
Figure 124
which is burst by the system asserting BRDY#.
10.4.6.1

Snoop under AHOLD during Pseudo-Locked Cycles

AHOLD can fracture a 64-bit transfer if it is a non-burst cycle. If the 64-bit cycle is
burst, as shown in
does the snoop write-back cycle start.
®
Intel Quark SoC X1000 Core
Developer's Manual
242
T1 T1 T2 T2
Write-Back
shows a 64-bit floating-point operand or Segment Descriptor read cycle,
Figure 124, the entire transfer goes to completion and only then
®
Intel
T2 T2 T1 T1
1st Flush
Acknowledge
Quark Core—Bus Operation
T2 T1 T2 T1 T1
2nd Flush
Acknowledge
242202-160
October 2013
Order Number: 329679-001US