Intel Quark SoC X1000 Core Developer's Manual page 113

Protected Mode Architecture—Intel
3. Push the legacy segment register values onto the new stack, in the order: GS, FS,
DS, ES. These are pushed as 32-bit quantities, with undefined values in the upper
16 bits. Then, load these four registers with null selectors (0).
4. Push the old stack pointer onto the new stack by pushing the SS register (as
32-bits, high bits undefined), then pushing the 32-bit ESP register saved above.
5. Push the 32-bit FLAGS register saved in step 1.
6. Push the old instruction pointer onto the new stack by pushing the CS register (as
32-bits, high bits undefined), then pushing the 32-bit EIP register.
7. Load the new CS:EIP value from the interrupt gate, and begin execution of the
interrupt routine in Protected Mode.
The transition out of Virtual 8086 Mode performs a level change and stack switch, in
addition to changing back to Protected Mode. In addition, all of the legacy segment
register images are stored on the stack (behind the SS:ESP image), and then loaded
with null (0) selectors before entering the interrupt handler. This permits the handler to
safely save and restore the DS, ES, FS, and GS registers. This is needed so that
interrupt handlers that do not care about the mode of the interrupted program can use
the same prolog and epilog code for state saving (i.e., push all registers in prolog, pop
all in epilog), regardless of whether or not a "native" mode or Virtual 8086 Mode
program was interrupted. Restoring null selectors to these registers before executing
the IRET instruction does not cause a trap in the interrupt handler. Interrupt routines
that obtain values from the segment registers or return values to segment registers
have to obtain/return them from the register images pushed onto the new stack. They
need to know the mode of the interrupted program in order to know where to
find/return segment registers, and also to know how to interpret segment register
values.
October 2013
Order Number: 329679-001US
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Quark Core
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Intel Quark SoC X1000 Core
Developer's Manual
113