Intel Quark SoC X1000 Core Developer's Manual page 274

Table 89. Clock Count Summary (Sheet 8 of 13)
Instruction
RET = Return from CALL
intersegment
to same level
to outet lever
intersegment adding
imm. to SP
to same level
to outer level
JMP = Unconditional Jump
Direct intersegment
to same level
thru Call Gate to same level
thru TSS
thru Task Gate
Indirect intersegment
to same level
thru Call Gate to same level
thru TSS
thru Task Gate
BIT MANIPULATION
BT = Test Bit
register, immediate
memory, immediate
reg1, reg2
memory, reg
Instruction
BTS = Test Bit and Set
BTR = Test Bit and Reset
BTC = Test Bit and
Complement
register, immediate
memory, immediate
reg1, reg2
memory, reg
BSF = Scan Bit Forward
reg1, reg2
memory, reg
BSR = Scan Bit Reverse
reg1, reg2
memory, reg
Note: See
®
Intel Quark SoC X1000 Core
Developer's Manual
274
1100 1010
1100 1010 : 16-bit disp.
1110 1010 : unsigned full offset, selector
1111 1111 : mod 011 r/m
0000 1111 : 1011 1010 : 11 100 reg :
imm. 8-bit data
0000 1111 : 1011 1010 : mod 100 r/m :
imm. 8-bit data
0000 1111 : 1010 0011 : 11 reg2 reg1
0000 1111 : 1010 0011 : mod reg r/m
TTT
101
110
111
0000 1111 : 1011 1010 : 11 TTT reg
imm. 8-bit data
0000 1111 : 1011 1010 : mod
imm. 8-bit data
0000 1111 : 10TT T011 : 1 1 reg2 reg1
0000 1111 : 10TT T011 : mod
0000 1111 : 1011 1100 : 11 reg2 reg1
0000 1111 : 1011 1100 : mod reg r/m
0000 1111 : 1011 1101 : 11 reg2 reg1
0000 1111 : 1011 1101 : mod reg r/m
Table 92 for notes and abbreviations for items in this table.
®
Intel Quark Core—Instruction Set Summary
Cache
Format
42+TS
43+TS
41+TS
42+TS
TTT r/m
reg r/m
6/103
7/104
Penalty
if
Notes
Hit Cache
Miss
13 8 R,7
17 9 P,9
35 12 P,9
14 8 R,7
18 9 P,9
36 12 P,9
17 2 R,7,22
19 3 P,9
32 6 P,9
3 P,10,9
3 P,10,9,
13 9 R,7,9
18 10 P,9
31 13 P,9
10 P,10,9
10 P,10,9,
3
3 1
3
8 2
6
8 U/L
6
13 U/L
MN/MX,
6/42
12
7/43 2 MN/MX, 15
MN/MX, 14
1 MN/MX, 15
October 2013
Order Number: 329679-001US