Reordering Of A Reads With Write Buffers - Intel Quark SoC X1000 Core Developer's Manual

Writes are driven onto the external bus in the same order in which they are received by
the write buffers. Under certain conditions, a memory read can go onto the external
bus before the memory writes pending in the buffer, even though the writes occurred
earlier in the program execution.
A memory read is reordered in front of all writes in the buffers only under the following
conditions: If all writes pending in the buffers are cache hits and the read is a cache
miss. Under these conditions, the Intel
external memory location that needs to be updated by one of the pending writes.
Reordering of a read with the writes pending in the buffers can only occur once before
all the buffers are emptied. Reordering read once maintains cache consistency.
Consider the following example: The processor writes to location X. Location X is in the
internal cache, so it is updated there immediately. However, the bus is busy, so the
write out to main memory is buffered (see
reads to location X are cache hits and the most up-to-date data is read.
Figure 70.

Reordering of a Reads with Write Buffers

The next instruction causes a read to location Y. Location Y is not in the cache (a cache
miss). Because the write in the write buffer is a cache hit, the read is reordered. When
location Y is read, it is put into the cache. The possibility exists that location Y will
replace location X in the cache. If this is true, location X would no longer be cached
(see Figure
Figure 71. Reordering of a Reads with Write Buffers
Cache consistency has been maintained up to this point. If a subsequent read is to
location X (now a cache miss) and it was reordered in front of the buffered write to
location X, stale data would be read. This is why only one read is allowed to be
reordered. Once a read is reordered, all writes in the write buffer are flagged as cache
misses to ensure that no more reads are reordered. Because one of the conditions to
reorder a read is that all writes in the write buffer must be cache hits, no further
reordering is allowed until all flagged writes propagate to the bus. Similarly, if an
invalidation cycle is run, all entries in the write buffer are flagged as cache misses.
In multiple processor systems and/or systems using DMA techniques such as bus
snooping, locked semaphores should be used to maintain cache consistency.
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Intel Quark SoC X1000 Core
Developer's Manual
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Intel® Quark
Core Cache
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Core Cache
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Intel Quark Core—Hardware Interface
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Quark SoC X1000 Core does not read from an
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October 2013
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