Cache Flush (Flush#); Hit/Miss To A Modified Line (Hitm#); Cache# Vs. Other Intel Quark Core Signals - Intel Quark SoC X1000 Core Developer's Manual

Table 50. Differences between CACHE# and PCD (Sheet 2 of 2)
Snoop-forced write-back
S-state write-through
I-state write-through
Notes:
1. Includes line fills and non-cacheable reads. During locked read cycles CACHE# is inactive. The non-
cacheable reads may or may not be burst.
2. Due to the non-allocate on write policy, this includes both cacheable and non-cacheable writes. PCD
distinguishes between the two, but CACHE# does not.
3. This behavior is the same as the existing specification of the Intel
through mode.
Table 51. CACHE# vs. Other Intel
Pin Symbol
ADS#
RDY#, BRDY#
HLDA, BOFF#
KEN#
9.2.17.2

Cache Flush (FLUSH#)

FLUSH# is an existing pin that operates differently if the processor is configured for
Enhanced Bus mode (write-back) operation. In Enhanced Bus mode, FLUSH# is treated
as an interrupt and acts similarly to the WBINVD instruction. It is sampled at each
clock, but is recognized only on an instruction boundary. Pending writes are completed
before FLUSH# is serviced, and all prefetching is stopped. Depending on the number of
modified lines in the cache, the flush could take up to a minimum of 1280 bus clocks or
2560 processor clocks and a maximum of 5000+ bus clocks to scan the cache, perform
the write backs, invalidate the cache and run two special cycles. After all modified lines
are written back to memory, two special bus cycles, the first flush ACK cycle and the
second flush ACK cycle, are issued, in that order. These cycles differ from the special
cycles issued after WBINVD only in that address line 2 = 1. SRESET, STPCLK#, INTR,
NMI and SMI# are not recognized during a flush write-back, whereas BOFF#, AHOLD
and HOLD are recognized.
FLUSH# may be asserted just for a single clock or may be retained asserted, but
should be de-asserted at or prior to the RDY# returned from the first flush ACK special
bus cycle. If asserted during INVD or WBINVD, FLUSH# is recognized. If asserted
simultaneously with SMI#, then SMI# is recognized after FLUSH# is serviced.
FLUSH# may be driven at any time. If driven during SRESET, it must be held for one
clock after SRESET is de-asserted to be recognized.
9.2.17.3

Hit/Miss to a Modified Line (HITM#)

HITM# is a cache coherency protocol pin that is driven only in Enhanced Bus mode.
When a snoop cycle is generated (with INV = 0 or INV = 1), HITM# indicates whether
the processor contains the snooped line in the M-state. HITM# asserted indicates that
the line will be written back in total, unless the processor is already generating a
replacement write-back of the same line.
HITM# is valid on the bus two system clocks after EADS# is asserted on the bus. If
asserted, HITM# remains asserted until the last RDY# or BRDY# of the snoop write-
back cycle is returned. It is de-asserted before the next ADS# (see
®
Intel Quark SoC X1000 Core
Developer's Manual
162
(2)
®
Quark Core Signals
CACHE# is driven to valid state with ADS#.
CACHE# is de-asserted with the first RDY# or BRDY#.
CACHE# floats under these signals.
The combination of CACHE# and KEN# determines if a read miss is converted into a
cache line fill.
®
Intel Quark Core—Hardware Interface
low
high
high
®
Quark SoC X1000 Core in write-
Relation To This Signal
Order Number: 329679-001US
low
(3)
same as PCD
(3)
same as PCD
Table 52).
October 2013