Update-Dr State; Select-Ir-Scan State; Capture-Ir State; Shift-Ir State - Intel Quark SoC X1000 Core Developer's Manual

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Testability—Intel Quark Core
B.3.1.9

Update-DR State

The JTAG register is provided with a latched parallel output to prevent changes at the
parallel output while data is shifted in response to the EXTEST and SAMPLE/PRELOAD
instructions. When the TAP controller is in this state and the JTAG register is selected,
data is latched onto the parallel output of this register from the shift-register path on
the falling edge of TCK. The data held at the latched parallel output does not change
other than in this state.
All test data registers selected by the current instruction retains its previous value
during this state. The instruction does not change in this state.
B.3.1.10

Select-IR-Scan State

This is a temporary controller state. The test data register selected by the current
instruction retains its previous value. If TMS is held low and a rising edge is applied to
TCK when in this state, the controller moves into the Capture-IR state, and a scan
sequence for the instruction register is initiated. If TMS is held high and a rising edge is
applied to TCK, the controller moves to the Test-Logic-Reset state.
The instruction does not change in this state.
B.3.1.11

Capture-IR State

In this controller state the shift register contained in the instruction register loads the
fixed value "0001" on the rising edge of TCK.
The test data register selected by the current instruction retains its previous value
during this state. The instruction does not change in this state. When the controller is in
this state and a rising edge is applied to TCK, the controller enters the Exit1-IR state if
TMS is held high, or the Shift-IR state if TMS is held low.
B.3.1.12

Shift-IR State

In this state the shift register contained in the instruction register is connected between
TDI and TDO and shifts data one stage towards its serial output on each rising edge of
TCK.
The test data register selected by the current instruction retains its previous value
during this state. The instruction does not change in this state.
When the controller is in this state and a rising edge is applied to TCK, the controller
enters the Exit1-IR state if TMS is held high, or remains in the Shift-IR state if TMS is
held low.
B.3.1.13

Exit1-IR State

This is a temporary state. While in this state, if TMS is held high, a rising edge applied
to TCK causes the controller to enter the Update-IR state, which terminates the
scanning process. If TMS is held low and a rising edge is applied to TCK, the controller
enters the Pause-IR state.
The test data register selected by the current instruction retains its previous value
during this state. The instruction does not change in this state.
B.3.1.14

Pause-IR State

The pause state allows the test controller to temporarily halt the shifting of data
through the instruction register.
October 2013
Order Number: 329679-001US
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Intel Quark SoC X1000 Core
Developer's Manual
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