Intel ® Quark Soc X1000 Cpuid - Intel Quark SoC X1000 Core Developer's Manual

Table 102. CPUID with PAE/XD/SMEP features implemented (Sheet 2 of 2)
EAX value Register
EAX,EBX,
0x80000002-
0x80000007
ECX,EDX
0x80000008 EAX
EBX,ECX,EDX
† When the value of Limit CPUID Maxval (bit 22 of IA32_MISC_ENABLE) is set to 1, all basic leaves above 3 should be
invisible. In this case, leaf 7 returns all zeros.
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Table 103. Intel Quark SoC X1000 CPUID
Initial EAX Value
0x0;
When IA32_MISC_ENABLES
[22]=1
0x1
0x80000000
0x8000_0001
0x8000_0008
The Intel
information available to the system software about the family, model, and stepping of
the processor. Support of this instruction is indicated by the ability of system software
to write and read the bit in position EFLAGS.21, referred to as the EFLAGS.ID bit. The
actual state of the EFLAGS.ID bit is irrelevant to the hardware. This bit is reset to zero
upon device reset (RESET and SRESET) for compatibility with legacy processor designs.
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Intel Quark SoC X1000 Core
Developer's Manual
310
Return value
0x0
0x2020
0x0
Basic CPUID Information;
Return Value
EAX=0x2;
EBX "Genu"
ECX "ntel"
EDX "ntel"
EAX = 590
ECX=All 0's
EBX
EDX = Value depends on
the RTL Knob
EAX=0x80000008;
EBX=ECX=EDX=All 0's
EDX[31:0] = 0x000100000;
EAX=EBX=ECX=0
EAX[31:0] = 0x00002020
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Quark SoC X1000 Core implements the CPUID instruction to make
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Intel Quark Core—Feature Determination
Information provided about the processor
Bit 7-0: physical address width
Bit 15-8: linear address bits
Description
Family ID = 0x5, Model = 0x9, Stepping ID = 0x0
[7:0] = Brand Index = All 0's.
[15:8] = 8'b0000_0010; CLFLUSH line size;
[23:16] = 8'b0000_0001;
Max. no.of addressable ID's for logical processors in this physical
package.
[0] = FPU on-chip
[1] = Virtual 8086 Mode enhancements.
[3] = PSE = Page Size Exntension; Large Pages of size 4MB are
supported, including CR4.PSE
[4] = TSC = Time Stamp Counter; RDTSC instruction is supported,
including CR4.TSD for controlling privilege.
[5] = MSR = Model Specific Register RDMSR/WRMSR Instructions
[6] = PAE = Physical Address Extension
[8] = CMXCHG8B Instruction Support
[9] = APIC = APIC on Chip
[13] = PGE = Page Global Bit
[31] = PBE = Pending Break Event
When CPUID executes with EAX set to 80000000H, the processor
returns the highest value the processor recognizes for returning
extended processor information. The value is returned in the EAX
register.
When PAE is enabled.
EAX[7:0] = Physical Address Bits;0x20h; EAX[15:8] = Virtual
Address Bits; 0x20h
October 2013
Order Number: 329679-001US