2Shutdown Indication Cycle; 3Stop Grant Indication Cycle; Stop Grant Bus Cycle; Special Bus Cycle Encoding - Intel Quark SoC X1000 Core Developer's Manual

®
Bus Operation—Intel Quark Core
10.3.11.2 Shutdown Indication Cycle
The Intel
attempting to process a double fault. A shutdown indication cycle is performed to
indicate that the processor has entered a shutdown state. The shutdown indication
cycle is identified by the bus definition signals in special bus cycle state and a byte
address of 0.
10.3.11.3 Stop Grant Indication Cycle
A special Stop Grant bus cycle is driven to the bus after the processor recognizes the
STPCLK# interrupt. The definition of this bus cycle is the same as the HALT cycle
definition for the Intel
bus cycle drives the value 0000 0010H on the address pins. The system hardware must
acknowledge this cycle by asserting RDY# or BRDY#. The processor does not enter the
Stop Grant state until either RDY# or BRDY# has been asserted. (See
The Stop Grant Bus Cycle is defined as follows:
M/IO# = 0, D/C# = 0, W/R# = 1, Address Bus = 0000 0010H (A4 = 1), BE[3:0]# =
1011, Data bus = undefined.
The latency between a STPCLK# request and the Stop Grant bus cycle is dependent on
the current instruction, the amount of data in the processor write buffers, and the
system memory performance.
Table 68.

Special Bus Cycle Encoding

First Flush Ack Cycle†
Second Flush Ack Cycle†
Stop Grant Ack Cycle
† These cycles are specific to the Write-Back Enhanced Intel
Figure 108. Stop Grant Bus Cycle
CLK
STPCLK#
ADDR Data
BRDY# or RDY#
October 2013
Order Number: 329679-001US
®
Quark SoC X1000 Core shuts down as a result of a protection fault while
®
Quark SoC X1000 Core, with the exception that the Stop Grant
Cycle Name M/IO#
Write-Back†
Flush†
Shutdown
HALT
T T
su hd
D/C# W/R#
0 0 1
0 0 1
0 0 1
0 0 1
0 0 1
0 0 1
0 0 1
®
Quark SoC X1000 Core.
Figure 108.)
BE[3:0]# A4-A2
0111 000
0111 001
1101 000
1101 001
1110 000
1011 000
1011 100
Stop Grant Cycle
A4401-01
®
Intel Quark SoC X1000 Core
Developer's Manual
221