System Management Interrupt Processing; Basic Smi# Interrupt Service - Intel Quark SoC X1000 Core Developer's Manual

SMBASE
Context
Context Switch
8.3

System Management Interrupt Processing

The system interrupts the normal program execution and invokes SMM by generating a
System Management Interrupt (SMI#) to the processor. The processor services the
SMI# by executing the following sequence (see
1. The processor asserts SMIACT#, indicating to the system that it should enable the
SMRAM.
2. The processor saves its state (context) to SMRAM, starting at default address
location 3FFFFH, proceeding downward in a stack-like fashion.
3. The processor switches to the System Management Mode processor environment (a
pseudo-real mode).
Figure 53.

Basic SMI# Interrupt Service

SMI#
Instr Instr Instr
#1 #2 #3
SMI#
SMIACT#
4. The processor then jumps to the default absolute address of 38000H in SMRAM to
execute the SMI# handler. This SMI# handler performs the system management
activities.
5. The SMI# handler then executes the RSM instruction (which restores the
processors context from SMRAM), de-asserts the SMIACT# signal, and then returns
control to the previously interrupted program execution.
Note: The above sequence is valid for the default SMBASE value only. See the following
sections for a description of the SMBASE register and SMBASE relocation.
®
Intel Quark SoC X1000 Core
Developer's Manual
128
®
Intel Quark Core—System Management Mode (SMM) Architectures
Control register that contains the address of the SMRAM space.
The processor state just before the processor invokes SMM. The
context normally consists of the processor registers that fully
represent the processor state.
The process of either saving or restoring the context. The SMM
discussion refers to the context switch as the process of
saving/restoring the context while invoking/exiting SMM,
respectively.
State Slave SMM Handler
Flush cache Cache must
be empty
Figure 53):
Instr Instr
#4
State Resume
RSM
Cache must
be empty
Order Number: 329679-001US
#5
A5237-01
October 2013