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Contents-Intel
Quark Core
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I/O Instruction Restart............................................................................................ 139
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SMM Base Location ................................................................................................ 140
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SMRAM Usage ....................................................................................................... 141
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SMRAM Location .................................................................................................... 142
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Cached SMM ......................................................................................................... 143
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Non-Cached SMM................................................................................................... 144
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Write-Back Enhanced Intel
SMRAM upon Entry and Exit of Cached SMM .............................................................. 145
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Reordering of a Reads with Write Buffers................................................................... 168
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Pin States During RESET ......................................................................................... 172
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Stop Clock Protocol ................................................................................................ 175
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Intel
Quark SoC X1000 Core Stop Clock State Machine ............................................. 178
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Bus Configuration) ................................................................................................. 181
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Quark Core with DMA .......................................................................... 194
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Basic 2-2 Bus Cycle ................................................................................................ 197
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Basic 3-3 Bus Cycle ................................................................................................ 198
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Burst Cacheable Cycle ............................................................................................ 204
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Effect of Changing KEN# ......................................................................................... 205
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Slow Burst Cycle .................................................................................................... 206
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Interrupted Burst Cycle........................................................................................... 208
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8-Bit Bus Size Cycle ............................................................................................... 210
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Locked Bus Cycle ................................................................................................... 212
100 Pseudo Lock Timing................................................................................................ 213
102 Typical Internal Cache Invalidation Cycle................................................................... 214
105 HOLD/HLDA Cycles................................................................................................. 218
106 HOLD Request Acknowledged during BOFF# .............................................................. 219
108 Stop Grant Bus Cycle.............................................................................................. 221
109 Restarted Read Cycle.............................................................................................. 222
111 Bus State Diagram ................................................................................................. 224
112 Basic Burst Read Cycle ........................................................................................... 227
October 2013
Order Number: 329679-001US
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Quark SoC X1000 Core Cache Flushing for Overlaid
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Quark SoC X1000 Core Stop Clock State Machine
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Quark Core System ................................................................... 193
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Intel
Quark SoC X1000 Core
Developer's Manual
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