Privilege Level Transfers; Descriptor Types Used For Control Transfer - Intel Quark SoC X1000 Core Developer's Manual

Any time an instruction loads data segment registers (DS, ES, FS, GS) the Intel
SoC X1000 Core makes protection validation checks. Selectors loaded in the DS, ES,
FS, GS registers must refer only to data segments or readable code segments. (The
data access rules are specified in
readable conforming code segments, that can be accessed at any privilege level.)
Finally, the privilege validation checks are performed. The CPL is compared to the EPL,
and if the EPL is more privileged than the CPL, an exception 13 (general protection
fault) is generated.
The rules for the stack segment are slightly different than those for data segments.
Instructions that load selectors into the SS must refer to data segment descriptors for
writeable data segments. The DPL and RPL must equal the CPL. All other descriptor
types and privilege level violations cause exception 13. A stack not present fault causes
exception 12. Note that an exception 11 is used for a not-present code or data
segment.
6.3.4

Privilege Level Transfers

Inter-segment control transfers occur when a selector is loaded in the CS register. In a
typical system, most of these transfers are the result of a call or a jump to another
routine. There are five types of control transfers, which are summarized in
Many of these transfers result in a privilege level transfer. Changing privilege levels is
done only via control transfers, by using gates, task switches, and interrupt or trap
gates.
Control transfers can only occur if the operation that loaded the selector references the
correct descriptor type. Any violation of these descriptor usage rules causes an
exception 13 (e.g., JMP through a call gate, or IRET from a normal subroutine call).
To provide further system security, all control transfers are also subject to the privilege
rules.
Table 28.

Descriptor Types Used for Control Transfer

Control Transfer Types
Intersegment within the same privilege
level
Intersegment to the same or higher
privilege level
Interrupt within task may change CPL
Intersegment to a lower privilege level
(changes task CPL)
Task Switch
Notes:
1. NT (Nested Task bit of flag register) = 0
2. NT (Nested Task bit of flag register) = 1
®
Intel Quark SoC X1000 Core
Developer's Manual
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®
Intel Quark Core—Protected Mode Architecture
Section 6.3.2. The only exception to those rules is
Operation Types
JMP, CALL, RET, IRET
CALL
Interrupt Instruction,
Exception, External
Interrupt
RET, IRET(1)
CALL, JMP
CALL, JMP
IRET(2)
Interrupt Instruction,
Exception, External
Interrupt
®
Table
Descriptor Descriptor
Referenced Table
Code Segment GDT/LDT
Call Gate GDT/LDT
Trap or Interrupt
IDT
Gate
Code Segment GDT/LDT
Task State
GDT
Segment
Task Gate GDT/LDT
Task Gate IDT
October 2013
Order Number: 329679-001US
Quark
28.