Smm And Second-Level Write Buffers; Nested Smi#S And I/O Restart; Smm Software Considerations; Smm Code Considerations - Intel Quark SoC X1000 Core Developer's Manual

System Management Mode (SMM) Architectures—Intel
least 20 CLK cycles after SMIACT# is de-asserted. Be careful not to block the global
system RESET, which may be necessary to recover from a system crash.
2. During execution of the RSM instruction to exit SMM, there is a small time window
between the de-assertion of SMIACT# and the completion of the RSM microcode. If
SRESET is asserted during this window, it is possible that the SMRAM space will be
violated. The system designer must guarantee that SRESET is blocked until at least
20 processor clock cycles after SMIACT# has been driven inactive.
3. Any request for a processor SRESET for the purpose of switching the processor
from Protected Mode to Real Mode must be acknowledged after the processor has
exited SMM. In order to maintain software transparency, the system logic must
latch any SRESET signals that are blocked during SMM.
8.6.5

SMM and Second-Level Write Buffers

Before the Intel
buffers. This is necessary so that the data in the write buffers is written to normal
memory space, not SMM space. Once the processor is ready to begin writing an SMM
state save to SMRAM, it asserts SMIACT#. SMIACT# may be driven active by the
processor before the system memory controller has had an opportunity to empty the
second-level write buffers.
To prevent the data from these second level write buffers from being written to the
wrong location, the system memory controller must direct the memory write cycles to
either SMM space or normal memory space. This can be accomplished by saving the
status of SMIACT# along with the address for each word in the write buffers.
8.6.6

Nested SMI#s and I/O Restart

Special care must be taken when executing an SMM handler for the purpose of
restarting an I/O instruction. When the processor executes a RSM instruction with the
I/O restart slot set, the restored EIP is modified to point to the instruction immediately
preceding the SMI# request, so that the I/O instruction can be re-executed. If a new
SMI# request is received while the processor is executing an SMM handler, the
processor services this SMI# request before restarting the original I/O instruction. If
the I/O restart slot is set when the processor executes the RSM instruction for the
second SMM handler, the RSM microcode decrements the restored EIP again. EI,
therefore, points to an address different than the originally interrupted instruction, and
the processor begins execution of the interrupted application code at an incorrect entry
point.
To prevent this problem, the SMM handler routine must not set the I/O restart slot
during the second of two consecutive SMM handlers.
8.7

SMM Software Considerations

8.7.1

SMM Code Considerations

The default operand size and the default address size are 16 bits; however, operand-
size override and address-size override prefixes can be used as needed to directly
access data anywhere within the 4-Gbyte logical address space.
With operand-size override prefixes, the SMM handler can use jumps, calls, and returns
to transfer control to any location within the 4-Gbyte space. Note, however, the
following restrictions:
• Any control transfer that does not have an operand-size override prefix truncates
EIP to 16 low-order bits.
October 2013
Order Number: 329679-001US
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Quark Core
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Quark SoC X1000 Core enters SMM, it empties its internal write
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Intel Quark SoC X1000 Core
Developer's Manual
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