Signal Descriptions - Intel Quark SoC X1000 Core Developer's Manual

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Signal Descriptions—Intel
Appendix A Signal Descriptions
For pin diagrams and pin locations, refer to the individual processor datasheets.
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Table 95. Intel Quark SoC X1000 Core Pin Descriptions (Sheet 1 of 5)
Symbol Type
Clock provides the fundamental timing and the internal operating frequency for the Intel
CLK I
All external timing parameters are specified with respect to the rising edge of CLK.
The Address Lines A[31:2], together with the byte enables signals BE[3:0]#, define the physical area of
A[31:4], I/O memory or input/output space accessed. Address lines A[31:4] are used to drive addresses to the
A[3:2] O processor to perform cache line invalidations. Input signals must meet setup and hold times t22 and t23.
A[31:2] are not driven during bus or address hold.
The Byte Enable signals indicate active bytes during read and write cycles. During the first cycle of a
cache fill, the external system should assume that all byte enables are active. BE3# applies to D[31:24],
BE[3:0]# O
BE2# applies to D[23:16], BE1# applies to D[15:8] and BE0# applies to D[7:0]. BE[3:0]# are active low
and are not driven during bus hold.
The Data Lines D[7:0] define the least significant byte of the data bus and lines D[31:24] define the
D[31:0] I/O most significant byte of the data bus. These signals must meet setup and hold times t22 and t23 for
proper operation on reads. These pins are driven during the second and subsequent clocks of write cycles.
One Data Parity pin exists for each byte of the data bus. Data parity is generated on all write data cycles
with the same timing as the data driven by the Intel
back into the processor on the data parity pins with the same timing as read information to ensure that
the correct parity check status is indicated by the Intel
DP[3:0] I/O
not affect program execution.
Input signals must meet setup and hold times t22 and t23. DP[3:0] should be connected to V
a pull-up resistor in systems that do not use parity. DP[3:0] are active high and are driven during the
second and subsequent clocks of write cycles.
The Memory/Input-Output, Data/Control and Write/Read lines are the primary bus definition
signals. These signals are driven valid as the ADS# signal is asserted.
M/IO#
M/IO# O
D/C# O
W/R# O
The bus definition signals are not driven during bus hold and follow the timing of the address bus. Refer to
Section 10.3.11, "Special Bus Cycles" on page
October 2013
Order Number: 329679-001US
Quark Core
ADDRESS BUS
DATA PARITY
D/C# W/R#
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
Name and Function
DATA BUS
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Quark Core. Even parity information must be driven
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Quark Core. The signals read on these pins do
Bus Cycle Initiated
0 Interrupt Acknowledge
1
0
1
0
1
0
1
220" for details.
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Quark Core.
CC
Halt/Special Cycle
I/O Read
I/O Write
Code Read
Reserved
Memory Read
Memory Write
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