13Bus States; Bus State Description - Intel Quark SoC X1000 Core Developer's Manual

10.3.13 Bus States
A bus state diagram is shown in
diagram is given in
Figure 111. Bus State Diagram
†
HOLD is only factored into this state transition if T
entered while a non-cacheable. non-burst, code prefetch was
in progress. Otherwise, ignore HOLD.
Table 69.

Bus State Description

State
Bus is idle. Address and status signals may be driven to undefined values, or the bus may be
Ti
floated to a high impedance state.
T1 First clock cycle of a bus cycle. Valid address and status are driven and ADS# is asserted.
Second and subsequent clock cycles of a bus cycle. Data is driven if the cycle is a write, or data is
T2
expected if the cycle is a read. RDY# and BRDY# are sampled.
T1b First clock cycle of a restarted bus cycle. Valid address and status are driven and ADS# is asserted.
Tb Second and subsequent clock cycles of an aborted bus cycle.
®
Intel Quark SoC X1000 Core
Developer's Manual
224
Figure
Table 69.
(RDY# Asserted + (BRDY# · BLAST#) Asserted) ·
(HOLD + AHOLD + No Request) · BOFF# Deasserted
Request Pending · (RDY# Asserted +
(BRDY# · BLAST#) Asserted) ·
HOLD Deasserted · AHOLD Deasserted · BOFF# Deasserted
Request Pending ·
HOLD Deasserted ·
Ti
AHOLD Deasserted ·
BOFF# Deasserted
®
Intel
111. A description of the signals used in the
T1
BOFF# Deasserted
BOFF#
Asserted
BOFF# Asserted
T
b
AHOLD Deasserted ·
BOFF# Deasserted ·
(HOLD) Deasserted
b
was
Means
Quark Core—Bus Operation
T2
BOFF#
Deasserted
T1b
†
240950–069
October 2013
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