Dynamic Bus Sizing During Cache Line Files; Data Bus Interface To 16- And 8-Bit Memories; Quark Soc X1000 Core Byte Enables - Intel Quark SoC X1000 Core Developer's Manual

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Bus Operation—Intel Quark Core
Figure 82.

Data Bus Interface to 16- and 8-Bit Memories

Intel® Quark
BS8#
BS16#
10.1.4

Dynamic Bus Sizing during Cache Line Files

BS8# and BS16# can be driven during cache line fills. The Intel
Core generates enough 8- or 16-bit cycles to fill the cache line. This can be up to
sixteen 8-bit cycles.
The external system should assume that all byte enables are asserted for the first cycle
of a cache line fill. The Intel
subsequent cycles in the line fill.
BHE# for the various combinations of the Intel
on both the first and subsequent cycles of the cache line fill. The "†" marks all
combinations of byte enables that are generated by the Intel
during a cache line fill.
Table 65. Generating A0, A1 and BHE# from the Intel
Enables (Sheet 1 of 2)
BE3#
1
1
1
†0
1
1
†0
1
October 2013
Order Number: 329679-001US
D[7:0] 8
D[15:8] 8
D[23:16] 8
Core
D[31:24] 8
(A[31:2], BE[3:0]#)
Address
Decode
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Quark SoC X1000 Core generates proper byte enables for
BE2# BE1# BE0#
1 1 0
1 0 0
0 0 0
0 0 0
1 0 1
0 0 1
0 0 1
0 1 1
Byte Swap
Logic
Byte Swap
Logic
Table 65 shows the appropriate A0 (BLE#), A1 and
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Quark SoC X1000 Core byte enables

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Quark SoC X1000 Core Byte
First Cache Fill Cycle
A0 A1 BHE#
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
32-Bit
Memory
16
16-Bit Memory
8
8-Bit Memory
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Quark SoC X1000
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Quark SoC X1000 Core
Any Other Cycle
A0 A1 BHE#
0 0 1
0 0 0
0 0 0
0 0 0
1 0 0
1 0 0
1 0 0
0 1 1
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Intel Quark SoC X1000 Core
Developer's Manual
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