Linear-Address Translation To A 2-Mbyte Page Using Pae Paging; Format Of A Pae Page-Directory Entry That Maps A 2-Mbyte Page - Intel Quark SoC X1000 Core Developer's Manual

Figure 42.

Linear-Address Translation to a 2-MByte Page using PAE Paging

Table 31.

Format of a PAE Page-Directory Entry that Maps a 2-MByte Page

Bit Position(s)
0 (P)
1 (R/W)
2 (U/S)
3 (PWT)
4 (PCD)
5 (A)
6 (D)
7 (PS)
8 (G)
11:9
12 (PAT)
20:13
(M–1):21
62:M
63 (XD)
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Intel Quark SoC X1000 Core
Developer's Manual
96
Present; must be 1 to map a 2-MByte page
Read/write; if 0, writes may not be allowed to the 2-MByte page referenced by this
entry
User/supervisor; if 0, user-mode accesses are not allowed to the 2-MByte page
referenced by this entry
Page-level write-through; indirectly determines the memory type used to access the
2-MByte page referenced by this entry
Page-level cache disable; indirectly determines the memory type used to access the
2-MByte page referenced by this entry
Accessed; indicates whether software has accessed the 2-MByte page referenced by
this entry
Dirty; indicates whether software has written to the 2-MByte page referenced by this
entry
Page size; must be 1 (otherwise, this entry references a page table; see
Global; if CR4.PGE = 1, determines whether the translation is global; ignored
otherwise
Ignored
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Reserved for Intel Quark SoC X1000 Core (must be 0)
Reserved (must be 0)
Physical address of the 2-MByte page referenced by this entry
Reserved (must be 0)
If IA32_EFER.NXE = 1, execute-disable (if 1, instruction fetches are not allowed from
the 2-MByte page controlled by this entry); otherwise, reserved (must be 0)
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Intel Quark Core—Protected Mode Architecture
Contents
Order Number: 329679-001US
Table 32)
October 2013