Exception Handling; Halt During Smm; Relocating Smram To An Address Above One Megabyte - Intel Quark SoC X1000 Core Developer's Manual

• Due to the Real Mode style of base-address formation, a far jump or call cannot
transfer control to a segment with a base address of more than 20 bits (one
Mbyte).
8.7.2

Exception Handling

Upon entry into SMM, external interrupts that require handlers are disabled (the IF bit
in the EFLAGS is cleared). This is necessary because, while the processor is in SMM, it
is running in a separate memory space. Consequently the vectors stored in the
interrupt descriptor table (IDT) for the prior mode are not applicable. Before allowing
exception handling (or software interrupts), the SMM program must initialize new
interrupt and exception vectors. The interrupt vector table for SMM has the same
format as for Real Mode. Until the interrupt vector table is correctly initialized, the SMM
handler must not generate an exception (or software interrupt). Even though hardware
interrupts are disabled, exceptions and software interrupts can occur. Only a correctly
written SMM handler can prevent internal exceptions. When new exception vectors are
initialized, internal exceptions can be serviced. The following restrictions apply:
1. Due to the Real Mode style of base address formation, an interrupt or exception
cannot transfer control to a segment with a base address of more that 20 bits.
2. An interrupt or exception cannot transfer control to a segment offset of more than
16 bits (64 Kbytes).
3. If exceptions or interrupts are allowed to occur, only the low order 16 bits of the
return address (EIP) are pushed onto the stack. If the offset of the interrupted
procedure is greater than 64 Kbytes, it is not possible for the interrupt/exception
handler to return control to that procedure. (One work-around could be to perform
software adjustment of the return address on the stack.)
4. The SMBASE relocation feature affects the way the processor returns from an
interrupt or exception during an SMI# handler.
8.7.3

Halt During SMM

HALT should not be executed during SMM, unless interrupts have been enabled (see
Section 8.7.2). Interrupts are disabled in SMM. INTR, NMI, and SMI# are the only
events that take the processor out of HALT.
8.7.4

Relocating SMRAM to an Address Above One Megabyte

Within SMM (or Real Mode), the segment base registers can be updated only by
changing the segment register. The segment registers contain only 16 bits, which
allows only 20 bits to be used for a segment base address (the segment register is
shifted left four bits to determine the segment base address). If SMRAM is relocated to
an address above one megabyte, the segment registers can no longer be initialized to
point to SMRAM.
These areas can be accessed by using address override prefixes to generate an offset
to the correct address. For example, if the SMBASE has been relocated immediately
below 16 Mbytes, the DS and ES registers are still initialized to 0000 0000H. We can
still access data in SMRAM by using 32-bit displacement registers:
mov esi,00FFxxxxH;64K segment
mov ax,ds:[esi]
®
Intel Quark SoC X1000 Core
Developer's Manual
148
®
Intel Quark Core—System Management Mode (SMM) Architectures
;immediately
;below 16 M
October 2013
Order Number: 329679-001US