Use Of Resume Flag (Rf) In Flag Register - Intel Quark SoC X1000 Core Developer's Manual

®
Debugging Support—Intel
BD (debug fault due to attempted register access when GD bit set)
This bit is set when the exception 1 handler is invoked due to an instruction that
attempts to read or write to the debug registers when the GD bit was set. If such an
event occurs, then the GD bit is automatically cleared when the exception 1 handler is
invoked, allowing the handler access to the debug registers.
BS (debug trap due to single-step)
This bit is set when the exception 1 handler is invoked due to the TF bit in the flag
register being set (for single-stepping).
BT (debug trap due to task switch)
This bit is set when the exception 1 handler was invoked due to a task switch that
occurs on a task having a Intel
the task switch into the new task occurs normally, but before the first instruction of the
task is executed, the exception 1 handler is invoked. With respect to the task switch
operation, the operation is considered to be a trap.
11.3.4

Use of Resume Flag (RF) in Flag Register

The Resume Flag (RF) in the flag word can suppress an instruction execution
breakpoint when the exception 1 handler returns to a user program at a user address
that is also an instruction execution breakpoint.
October 2013
Order Number: 329679-001US
Quark Core
®
Quark SoC X1000 Core TSS with the T bit set. Note
®
Intel Quark SoC X1000 Core
Developer's Manual
251