Intel ® Quark Soc X1000 Core Instructions; Cmpxchg8B - Compare And Exchange Bytes - Intel Quark SoC X1000 Core Developer's Manual

Instruction Set Summary—Intel
Table 88. Encoding of Floating-Point Instruction Fields
1 11011
2 11011
3 11011
4 11011
5 11011
15–11
Table Key:
OP = Instruction opcode,
possibly split into two fields OPA
and OPB
MF = Memory Format
00–32-bit real
01–32-bit integer
10–64-bit real
11–16-bit integer
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12.2.5 Intel
The instructions below were added to the Intel
and in hardware for RDTSC).
CMPXCHG8B
RDMSR
RDTSC
WRMSR
12.2.5.1

CMPXCHG8B - Compare and Exchange Bytes

Description
Compares the 64-bit value in EDX:EAX (or 128-bit value in RDX:RAX if operand size is
128 bits) with the operand (destination operand). If the values are equal, the 64-bit
value in ECX:EBX (or 128-bit value in RCX:RBX) is stored in the destination operand.
Otherwise, the value in the destination operand is loaded into EDX:EAX (or RDX:RAX).
The destination operand is an 8-byte memory location (or 16-byte memory location if
operand size is 128 bits). For the EDX:EAX and ECX:EBX register pairs, EDX and ECX
contain the high-order 32 bits and EAX and EBX contain the loworder 32 bits of a 64-bit
value. For the RDX:RAX and RCX:RBX register pairs, RDX and RCX contain the high-
order 64 bits and RAX and RBX contain the low-order 64 bits of a 128-bit value.
This instruction can be used with a LOCK prefix to allow the instruction to be executed
atomically. To simplify the interface to the processor's bus, the destination operand
receives a write cycle without regard to the result of the comparison. The destination
operand is written back if the comparison fails; otherwise, the source operand is
written into the destination. (The processor never produces a locked read without also
producing a locked write.)
October 2013
Order Number: 329679-001US
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Quark Core
First Byte
OPA 1
MF OPA
d P OPA
0 0 1
0 1 1
10 9 8
P = Pop
d = Destination
Quark SoC X1000 Core Instructions
CoMPare and eXCHanGe 8 Bytes
ReaD from Model-Specific Register
ReaD Time Stamp Counter
WRite to Model-Specific Register
Instruction
Second Byte
mod 1
mod OPB
1 1 OPB
1 1 1
1 1 1
7 6 5
0–Do not pop stack
1–Pop stack after operation
0–Destination is ST(0)
1–Destination is ST(i)
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Quark SoC X1000 Core (in microcode
Optional
Fields
OPB r/m s-i-b
r/m s-i-b
ST(i)
OP
OP
4 3 2 1 0
R XOR d=0–Destination (op)
Source
R XOR d=1–Source (op)
Destination
ST(i)= Register stack element i
000 = Stack top
001 = Second stack element
111 = Eighth stack element
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Intel Quark SoC X1000 Core
Developer's Manual
disp
disp
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