Intel ® Quark Soc X1000 Core Stop Clock State Machine - Intel Quark SoC X1000 Core Developer's Manual

are not recognized until one CLK after STPCLK# is de-asserted (see
While in the Stop Grant state, the processor does not recognize transitions on the
interrupt signals (SMI#, NMI, and INTR). Driving an active edge on either SMI# or NMI
does not guarantee recognition and service of the interrupt request following exit from
the Stop Grant state. However, if one of the interrupt signals (SMI#, NMI, or INTR) is
driven active while the processor is in the Stop Grant state, and held active for at least
one CLK after STPCLK# is de-asserted, the corresponding interrupt is serviced. The
®
Intel Quark SoC X1000 Core requires INTR to be held active until the processor issues
an interrupt acknowledge cycle in order to guarantee recognition (see
When the processor is in the Stop Grant state, the system can stop or change the CLK
input. When the CLK input to the processor is stopped or changed, the Intel
SoC X1000 Core requires the CLK input to be held at a constant frequency for a
minimum of 1 ms before de-asserting STPCLK#. This 1-ms time period is necessary so
that the PLL can stabilize, and it must be met before the processor returns to the Stop
Grant state.
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Figure 74. Intel Quark SoC X1000 Core Stop Clock State Machine
4. Auto HALT Power Down State
5. Stop Clock Snoop State
†
The system can change the input frequency within the
specified range or completely stop the CLK input frequency
The Intel
that state from the Normal or the Auto HALT Power Down state. When the Intel
SoC X1000 Core enters the Stop Grant state from the Stop Clock state or the Stop
Clock Snoop state, the processor does not generate a Stop Grant bus cycle.
®
Intel Quark SoC X1000 Core
Developer's Manual
178
CLK Running
I ~ 100 mA
CC
EADS#
STPCLK# asserted and
Stop Grant Bus cycle generated
One Clock Powerup
Perform Cache Invalidation
®
Quark SoC X1000 Core generates a Stop Grant bus cycle only when entering
Intel
HALT asserted and
1. Normal State
HALT Bus cycle
generated
INTR, NMI, SMI#,
RESET, SRESET
STPCLK# de-asserted and
HALT Bus cycle generated
2. Stop Grant State
EADS#
3. Stop Clock State
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Quark Core—Hardware Interface
Figure 75).
Figure 75).
®
Quark
Normal Execution
STPCLK# asserted and
Stop Grant Bus cycle
generated
Clock Running
I – 20 mA – 50 mA
CC
S CLK
TART
S CLK
+ PLL S L
TOP
TARTUP ATENCY
Internal Powerdown
†
CLK Changed
I ~ 100 mA
CC
®
October 2013
Order Number: 329679-001US
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