Intel ® Quark Soc X1000 Core Pin Descriptions - Intel Quark SoC X1000 Core Developer's Manual

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Table 95. Intel Quark SoC X1000 Core Pin Descriptions (Sheet 2 of 5)
Symbol Type
The Bus Lock pin indicates that the current bus cycle is locked. The Intel
bus hold when LOCK# is asserted (but address holds are allowed). LOCK# goes active in the first clock of
LOCK# O the first locked bus cycle and goes inactive after the last clock of the last locked bus cycle. The last locked
cycle ends when ready is asserted. LOCK# is active low and is not driven during bus hold. Locked read
cycles are not transformed into cache fill cycles when KEN# is asserted.
The Pseudo-Lock pin indicates that the current bus transaction requires more than one bus cycle to
complete. For the Intel
bits) and cache line fills (128 bits). For Intel
point long reads and writes (64 bits) also require more than one bus cycle to complete.
The Intel
been driven, regardless of whether RDY# or BRDY# have been asserted.
PLOCK# O
Normally PLOCK# and BLAST# are the inverse of each other. However, during the first bus cycle of a 64-
bit floating-point write (for Intel
BLAST# are asserted.
PLOCK# is a function of the BS8#, BS16# and KEN# inputs. PLOCK# should be sampled only in the clock
in which ready is asserted. PLOCK# is active low and is not driven during bus hold.
The Address Status output indicates that a valid bus cycle definition and address are available on the
ADS# O cycle definition lines and address bus. ADS# is driven active in the same clock in which the addresses are
driven. ADS# is active low and is not driven during bus hold.
The Non-burst Ready input indicates that the current bus cycle is complete. RDY# indicates that the
external system has presented valid data on the data pins in response to a read or that the external
system has accepted data from the Intel
bus is idle and at the end of the first clock of the bus cycle.
RDY# I
RDY# is active during address hold. Data can be returned to the processor while AHOLD is active.
RDY# is active low, and is not provided with an internal pull-up resistor. RDY# must satisfy setup and hold
times t16 and t17 for proper chip operation.
The Burst Ready input performs the same function during a burst cycle that RDY# performs during a
non-burst cycle. BRDY# indicates that the external system has presented valid data in response to a read
or that the external system has accepted data in response to a write. BRDY# is ignored when the bus is
idle and at the end of the first clock in a bus cycle.
BRDY# I BRDY# is sampled in the second and subsequent clocks of a burst cycle. The data presented on the data
bus is strobed into the processor when BRDY# is sampled asserted. When RDY# is asserted
simultaneously with BRDY#, BRDY# is ignored and the burst cycle is prematurely aborted.
BRDY# is active low and is provided with a small pull-up resistor. BRDY# must satisfy the setup and hold
times t16 and t17.
The Burst Last signal indicates that the next time BRDY# is asserted, the burst bus cycle is complete.
BLAST# O BLAST# is active for both burst and non-burst bus cycles. BLAST# is active low and is not driven during
bus hold.
The Reset input forces the Intel
begin execution of instructions until at least 1 ms after V
RESET I specifications. The RESET pin should remain active during this time to ensure proper processor operation.
RESET is active high. RESET is asynchronous but must meet setup and hold times t20 and t21 for
recognition in any specific clock.
The Maskable Interrupt indicates that an external interrupt has been generated. When the internal
interrupt flag is set in EFLAGS, active interrupt processing is initiated. The Intel
two locked interrupt acknowledge bus cycles in response to the INTR pin being asserted. INTR must
remain active until the interrupt acknowledges have been performed to ensure that the interrupt is
INTR I
recognized.
INTR is active high and is not provided with an internal pull-down resistor. INTR is asynchronous, but
must meet setup and hold times t20 and t21 for recognition in any specific clock.
The Non-Maskable Interrupt request signal indicates that an external non-maskable interrupt has been
generated. NMI is rising edge sensitive. NMI must be held low for at least four CLK periods before this
NMI I
rising edge. NMI is not provided with an internal pull-down resistor. NMI is asynchronous, but must meet
setup and hold times t20 and t21 for recognition in any specific clock.
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Intel Quark SoC X1000 Core
Developer's Manual
292
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Quark Core, examples of such operations are segment table descriptor reads (64
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Quark Core asserts PLOCK# until the addresses for the last bus cycle of the transaction have
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Quark Cores with on-chip Floating-Point Unit) both PLOCK# and
BUS CONTROL
BURST CONTROL
INTERRUPTS
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Quark Core to begin execution at a known state. The processor cannot
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Intel
Name and Function
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Quark Cores with an on-chip Floating-Point Unit, floating-
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Quark Core in response to a write. RDY# is ignored when the
and CLK have reached their proper DC and AC
CC
Quark Core—Signal Descriptions
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Quark Core does not allow a
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Quark Core generates
October 2013
Order Number: 329679-001US