Smm System Design Considerations; Smram Interface; Smram Usage - Intel Quark SoC X1000 Core Developer's Manual

System Management Mode (SMM) Architectures—Intel
To change the SMRAM base address and SMM jump vector location, the SMM handler
should modify the SMBASE slot. Upon executing an RSM instruction, the processor
reads the SMBASE slot and stores it internally. Upon recognition of the next SMI#
request, the processor uses the new SMBASE slot for the SMRAM dump and SMI# jump
vector.
If the modified SMBASE slot does not contain a 32-Kbyte aligned value, the RSM
microcode causes the processor to enter the shutdown state.
Figure 63.

SMRAM Usage

8.6

SMM System Design Considerations

8.6.1

SMRAM Interface

The hardware designed to control the SMRAM space must follow these guidelines:
1. A provision should be made to allow for initialization of SMRAM space during
system boot up. This initialization of SMRAM space must happen before the first
occurrence of an SMI# interrupt. Initializing the SMRAM space must include
installation of an SMM handler, and may include installation of related data
structures necessary for particular SMM applications. The memory controller
providing the interface to the SMRAM should provide a means for the initialization
code to manually open the SMRAM space.
2. A minimum initial SMRAM address space of 38000H-3FFFFH should be decoded by
the memory controller.
3. Alternate bus masters (such as DMA controllers) should not be allowed to access
SMRAM space. Only the processor, either through SMI# or during initialization,
should be allowed access to SMRAM.
4. In order to implement a zero-volt suspend function, the system must have access
to all of normal system memory from within an SMM handler routine. If the SMRAM
is going to overlay normal system memory, there must be a method of accessing
any system memory located underneath SMRAM.
There are two potential schemes for locating the SMRAM: either overlaid to an address
space on top of normal system memory, or placed in a distinct address space (see
Figure 64). When SMRAM is overlaid on top of normal system memory, the processor
output signal SMIACT# must be used to distinguish SMRAM from main system memory.
Additionally, if the overlaid normal memory is cacheable, both the processor internal
cache and any second-level caches must be empty before the first read of an SMM
handler routine. If the SMM memory is cacheable, the caches must be empty before
the first read of normal memory following an SMM handler routine. This is done by
flushing the caches, and is required to maintain cache coherency. When the default
SMRAM location is used, SMRAM is overlaid on top of system main memory (at 38000H
through 3FFFFH).
October 2013
Order Number: 329679-001US
®
Quark Core
SMRAM
SMBASE + 8000H
Start of State Slave
+ 7FFFH
SMM Handler Entry
SMBASE + 8000H
SMBASE
®
Intel Quark SoC X1000 Core
Developer's Manual
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