Stop Clock State; Auto Halt Power Down State; Stop Clock Snoop State (Cache Invalidations); Recognition Of Inputs When Exiting Stop Grant State - Intel Quark SoC X1000 Core Developer's Manual

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Hardware Interface—Intel
9.6.4.3

Stop Clock State

Stop Clock state is entered from the Stop Grant state by stopping the CLK input (either
logic high or logic low). None of the processor input signals should change state while
the CLK input is stopped. Any transition on an input signal (with the exception of INTR,
NMI and SMI#) before the processor has returned to the Stop Grant state results in
unpredictable behavior. If INTR is driven active while the CLK input is stopped, and held
active until the processor issues an interrupt acknowledge bus cycle, it is serviced in
the normal manner. The system design must ensure that the processor is in the correct
state prior to asserting cache invalidation or interrupt signals to the processor.
Figure 75.

Recognition of Inputs when Exiting Stop Grant State

CLK
STPCLK#
SMI#
The processor returns to the Stop Grant state after the CLK input has been running at a
constant frequency for a period of time equal to the PLL startup latency (see
Section 9.6.4.2). The CLK input can be restarted to any frequency between the
minimum and maximum frequency listed in the AC timing specifications.
9.6.4.4

Auto HALT Power Down State

The execution of a HALT instruction also causes the processor to automatically enter
the Auto HALT Power Down state. The processor issues a normal HALT bus cycle before
entering this state. The processor transitions to the Normal state on the occurrence of
INTR, NMI, SMI#, RESET, or SRESET.
The system can generate a STPCLK# while the processor is in the Auto HALT Power
Down state. The processor generates a Stop Grant bus cycle when it enters the Stop
Grant state from the HALT state.
When the system de-asserts the STPCLK# interrupt, the processor returns execution to
the HALT state. The processor generates a new HALT bus cycle when it re-enters the
HALT state from the Stop Grant state.
9.6.4.5

Stop Clock Snoop State (Cache Invalidations)

When the processor is in the Stop Grant state or the Auto HALT Power Down state, the
processor recognizes HOLD, AHOLD, BOFF# and EADS# for cache invalidation. When
the system asserts HOLD, AHOLD, or BOFF#, the processor floats the bus accordingly.
When the system then asserts EADS#, the processor transparently enters the Stop
Clock Snoop state and powers up for one full core clock in order to perform the
required cache snoop cycle. It then re-freezes the clock to the processor core and
returns to the previous state. The processor does not generate a bus cycle when it
returns to the previous state.
October 2013
Order Number: 329679-001US
Quark Core
NMI
A: Earliest time at which NMI or SMI# is recognized.
STPCLK# Sampled
T T
SU HD
A
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Intel Quark SoC X1000 Core
Developer's Manual
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