11Special Bus Cycles; 1Halt Indication Cycle; Interrupt Acknowledge Cycles - Intel Quark SoC X1000 Core Developer's Manual

Figure 107. Interrupt Acknowledge Cycles
CLK
ADS#
ADDR
RDY#
DATA
LOCK#
10.3.11 Special Bus Cycles
The Intel
instructions have been executed, or certain conditions have occurred internally. The
special bus cycles are identified by the status of the pins shown in
During these cycles the address bus is driven low while the data bus is undefined.
Two of the special cycles indicate halt or shutdown. Another special cycle is generated
when the Intel
instruction and could be used to flush an external cache. The Write Back cycle is
generated when the Intel
invalidate data cache) instruction and could be used to synchronize an external write-
back cache.
The external hardware must acknowledge these special bus cycles by asserting RDY#
or BRDY#.
10.3.11.1 HALT Indication Cycle
The Intel
HALT indication cycle is performed to signal that the processor has entered into the
HALT state. The HALT indication cycle is identified by the bus definition signals in
special bus cycle state and by a byte address of 2. BE0# and BE2# are the only signals
that distinguish HALT indication from shutdown indication, which drives an address of
0. During the HALT cycle, undefined data is driven on D[31:0]. The HALT indication
cycle must be acknowledged by RDY# asserted.
A halted Intel
enabled), NMI, or RESET is asserted.
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To Processor
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Quark SoC X1000 Core provides special bus cycles to indicate that certain
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Quark SoC X1000 Core executes an INVD (invalidate data cache)
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Quark SoC X1000 Core executes the WBINVD (write-back
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Quark SoC X1000 Core halts as a result of executing a HALT instruction. A
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Quark SoC X1000 Core resumes execution when INTR (if interrupts are
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Intel Quark Core—Bus Operation
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Table 68.
October 2013
Order Number: 329679-001US
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